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Message-ID: <CAMuHMdXHJ385isGd-x8u4sFm1w=rxOC89SUryYbSd34bijkb0g@mail.gmail.com>
Date: Fri, 13 May 2022 16:29:41 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Linus Walleij <linus.walleij@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Philipp Zabel <p.zabel@...gutronix.de>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Phil Edworthy <phil.edworthy@...esas.com>,
Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to
handle GPIO interrupt
Hi Prabhakar,
On Fri, May 13, 2022 at 3:56 PM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Fri, May 13, 2022 at 7:53 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Thu, May 12, 2022 at 7:36 PM Lad, Prabhakar
> > <prabhakar.csengg@...il.com> wrote:
> > > On Thu, May 12, 2022 at 8:39 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > > > On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > > > Add IRQ domian to RZ/G2L pinctrl driver to handle GPIO interrupt.
> > > > > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be
> > > > > used as IRQ lines at given time. Selection of pins as IRQ lines
> > > > > is handled by IA55 (which is the IRQC block) which sits in between the
> > > > > GPIO and GIC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > >
> > > > > static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> > > > > {
> > > > > struct device_node *np = pctrl->dev->of_node;
> > > > > struct gpio_chip *chip = &pctrl->gpio_chip;
> > > > > const char *name = dev_name(pctrl->dev);
> > > > > + struct irq_domain *parent_domain;
> > > > > struct of_phandle_args of_args;
> > > > > + struct device_node *parent_np;
> > > > > + struct gpio_irq_chip *girq;
> > > > > int ret;
> > > > >
> > > > > + parent_np = of_irq_find_parent(np);
> > > > > + if (!parent_np)
> > > > > + return -ENXIO;
> > > > > +
> > > > > + parent_domain = irq_find_host(parent_np);
> > > > > + of_node_put(parent_np);
> > > > > + if (!parent_domain)
> > > > > + return -EPROBE_DEFER;
> > > > > +
> > > > > ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
> > > > > if (ret) {
> > > > > dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
> > > > > @@ -1138,6 +1330,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> > > > > chip->base = -1;
> > > > > chip->ngpio = of_args.args[2];
> > > > >
> > > > > + girq = &chip->irq;
> > > > > + girq->chip = &rzg2l_gpio_irqchip;
> > > > > + girq->fwnode = of_node_to_fwnode(np);
> > > > > + girq->parent_domain = parent_domain;
> > > > > + girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
> > > > > + girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
> > > > > + girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
> > > > > + girq->ngirq = RZG2L_TINT_MAX_INTERRUPT;
> > > > > +
> > > >
> > > > I think you need to provide a .init_valid_mask() callback, as
> > > > gpiochip_irqchip_remove() relies on that for destroying interrupts.
> > > Are you suggesting the callback to avoid looping through all the GPIO pins?
> >
> > gpiochip_irqchip_remove() does:
> >
> > /* Remove all IRQ mappings and delete the domain */
> > if (gc->irq.domain) {
> > unsigned int irq;
> >
> > for (offset = 0; offset < gc->ngpio; offset++) {
> > if (!gpiochip_irqchip_irq_valid(gc, offset))
> > continue;
> >
> > irq = irq_find_mapping(gc->irq.domain, offset);
> > irq_dispose_mapping(irq);
> > }
> >
> > irq_domain_remove(gc->irq.domain);
> >
> > }
> >
> > The main thing is not about avoiding to loop through all GPIO pins,
> > but to avoid irq_{find,dispose}_mapping() doing the wrong thing.
> So in our case if we don't implement valid masks, that would mean all
> the pins are valid. irq_find_mapping() would return 0 if no mapping is
> found to the corresponding offset and irq_dispose_mapping() would
> simply return back without doing anything if virq == 0.(In this patch
> rzg2l_gpio_free() does call irq_{find,dispose}_mapping())
But "offset" is a number from the GPIO offset space (0-122), while
irq_find_mapping() expects a number from the domain's IRQ space,
which is only 0-31?
> > The loop is over all GPIO offsets, while not all of them are mapped
> > to valid interrupts. Does the above work correctly?
> >
> I haven't tested unloading the pinctrl driver which should call
> gpiochip_irqchip_remove() (we don't have remove call back for pinctrl
> driver)
>
> > > > However, the mask will need to be dynamic, as GPIO interrupts can be
> > > > mapped and unmapped to one of the 32 available interrupts dynamically,
> > > > right?
> > > Yep that's correct.
> > >
> > > > I'm not sure if that can be done easily: if gpiochip_irqchip_irq_valid()
> > > > is ever called too early, before the mapping is done, it would fail.
> > > >
> > > The mask initialization is a one time process and that is during
> > > adding the GPIO chip. At this stage we won't be knowing what will be
> > > the valid GPIO pins used as interrupts. Maybe the core needs to
> > > implement a callback which lands in the GPIO controller driver to tell
> > > if the gpio irq line is valid. This way we can handle dynamic
> > > interrupts.
> >
> > Upon closer look, I think the mask is a red herring, and we don't
> > need it.
> Agreed.
>
> > But we do need to handle the (possible) mismatch between GPIO
> > offset (index) and IRQ offset in the above code.
> >
> Agreed, do you see any possibility of the mismatch I have missed?
gpiochip_to_irq():
if (irq_domain_is_hierarchy(domain)) {
struct irq_fwspec spec;
spec.fwnode = domain->fwnode;
spec.param_count = 2;
spec.param[0] = gc->irq.child_offset_to_irq(gc, offset);
spec.param[1] = IRQ_TYPE_NONE;
return irq_create_fwspec_mapping(&spec);
}
Same here: in the absence of a child_offset_to_irq() callback,
the default gpiochip_child_offset_to_irq_noop() will be used,
assuming an identity mapping between GPIO numbers and IRQ
numbers.
So perhaps
1. you need to provide a child_offset_to_irq() callback,
2. gpiochip_irqchip_remove() needs to apply the child_offset_to_irq()
mapping too?
3. you do need the mask, or let child_offset_to_irq() an error code,
to avoid irq_{find,dispose}_mapping() handling non-existent irqs?
Or am I missing something?
I guess this is easy to verify by adding some debug prints to the code.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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