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Message-ID: <CAGXv+5FW59B1Dq8eH=5KjEdTxgT64GuvYZHZ9LnnTuaVrK3XpQ@mail.gmail.com>
Date: Mon, 16 May 2022 13:35:18 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>
Cc: rafael@...nel.org, viresh.kumar@...aro.org, robh+dt@...nel.org,
krzk+dt@...nel.org, matthias.bgg@...il.com,
jia-wei.chang@...iatek.com, roger.lu@...iatek.com,
hsinyi@...gle.com, khilman@...libre.com,
angelogioacchino.delregno@...labora.com, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
"Andrew-sh . Cheng" <andrew-sh.cheng@...iatek.com>
Subject: Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@...iatek.com> wrote:
>
> Add MediaTek CCI devfreq node for MT8183.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@...iatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 3 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 8953dbf84f3e..7ac9864db9de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,10 @@
>
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index 8d5bf73a9099..b035e06840e6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -230,6 +230,10 @@
> status = "okay";
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index cecf96b628b7..11caf3dd85cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -280,6 +280,13 @@
> };
> };
>
> + cci: cci {
> + compatible = "mediatek,mt8183-cci";
> + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> + clock-names = "cci_clock";
Binding says there should be two clocks: the actual clock that drives
CCI, and a stable "intermediate" clock to switch to during clock rate
changes. So I think this should look like:
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cci", "intermediate";
ChenYu
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.18.0
>
>
> _______________________________________________
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