| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAJF2gTR_qUnCe6Zeyhn9m=qAASMqXv7GAhqBhL604JKrUNCmcw@mail.gmail.com>
Date: Mon, 16 May 2022 14:45:13 +0800
From: Guo Ren <guoren@...nel.org>
To: Heiko Stuebner <heiko@...ech.de>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Wei Fu <wefu@...hat.com>, liush <liush@...winnertech.com>,
Atish Patra <atishp@...shpatra.org>,
Anup Patel <anup@...infault.org>,
Drew Fustini <drew@...gleboard.org>,
Christoph Hellwig <hch@....de>, Arnd Bergmann <arnd@...db.de>,
Chen-Yu Tsai <wens@...e.org>,
Maxime Ripard <maxime@...no.tech>,
Greg Favor <gfavor@...tanamicro.com>,
Andrea Mondelli <andrea.mondelli@...wei.com>,
Jonathan Behrens <behrensj@....edu>,
"Xinhaoqu (Freddie)" <xinhaoqu@...wei.com>,
Nick Kossifidis <mick@....forth.gr>,
Allen Baum <allen.baum@...erantotech.com>,
Josh Scheid <jscheid@...tanamicro.com>,
Richard Trauben <rtrauben@...il.com>,
Samuel Holland <samuel@...lland.org>,
Christoph Muellner <cmuellner@...ux.com>,
Philipp Tomsich <philipp.tomsich@...ll.eu>
Subject: Re: [PATCH 01/12] riscv: integrate alternatives better into the main architecture
Reviewed-by: Guo Ren <guoren@...nel.org>
On Thu, May 12, 2022 at 3:29 AM Heiko Stuebner <heiko@...ech.de> wrote:
>
> Right now the alternatives need to be explicitly enabled and
> erratas are limited to SiFive ones.
>
> We want to use alternatives not only for patching soc erratas,
> but in the future also for handling different behaviour depending
> on the existence of future extensions.
>
> So move the core alternatives over to the kernel subdirectory
> and move the CONFIG_RISCV_ALTERNATIVE to be a hidden symbol
> which we expect relevant erratas and extensions to just select
> if needed.
>
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@...ll.eu>
> ---
> arch/riscv/Kconfig | 9 +++++++++
> arch/riscv/Kconfig.erratas | 13 ++-----------
> arch/riscv/Kconfig.socs | 1 -
> arch/riscv/Makefile | 2 +-
> arch/riscv/errata/Makefile | 1 -
> arch/riscv/include/asm/alternative-macros.h | 7 ++++---
> arch/riscv/include/asm/alternative.h | 8 ++++++++
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/{errata => kernel}/alternative.c | 0
> arch/riscv/kernel/smpboot.c | 2 --
> arch/riscv/kernel/traps.c | 2 +-
> 11 files changed, 26 insertions(+), 20 deletions(-)
> rename arch/riscv/{errata => kernel}/alternative.c (100%)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f8a55d94016d..1ec07aa582a3 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -325,6 +325,15 @@ config NODES_SHIFT
> Specify the maximum number of NUMA Nodes available on the target
> system. Increases memory reserved to accommodate various tables.
>
> +config RISCV_ALTERNATIVE
> + bool
> + depends on !XIP_KERNEL
> + help
> + This Kconfig allows the kernel to automatically patch the
> + errata required by the execution platform at run time. The
> + code patching is performed once in the boot stages. It means
> + that the overhead from this mechanism is just taken once.
> +
> config RISCV_ISA_C
> bool "Emit compressed instructions when building Linux"
> default y
> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
> index 0aacd7052585..c521c2ae2de2 100644
> --- a/arch/riscv/Kconfig.erratas
> +++ b/arch/riscv/Kconfig.erratas
> @@ -1,18 +1,9 @@
> menu "CPU errata selection"
>
> -config RISCV_ERRATA_ALTERNATIVE
> - bool "RISC-V alternative scheme"
> - depends on !XIP_KERNEL
> - default y
> - help
> - This Kconfig allows the kernel to automatically patch the
> - errata required by the execution platform at run time. The
> - code patching is performed once in the boot stages. It means
> - that the overhead from this mechanism is just taken once.
> -
> config ERRATA_SIFIVE
> bool "SiFive errata"
> - depends on RISCV_ERRATA_ALTERNATIVE
> + depends on !XIP_KERNEL
> + select RISCV_ALTERNATIVE
> help
> All SiFive errata Kconfig depend on this Kconfig. Disabling
> this Kconfig will disable all SiFive errata. Please say "Y"
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index f6ef358d8a2c..85670dc9fe95 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -14,7 +14,6 @@ config SOC_SIFIVE
> select CLK_SIFIVE
> select CLK_SIFIVE_PRCI
> select SIFIVE_PLIC
> - select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL
> select ERRATA_SIFIVE if !XIP_KERNEL
> help
> This enables support for SiFive SoC platform hardware.
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 7d81102cffd4..a7ed47ce9311 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -103,7 +103,7 @@ endif
>
> head-y := arch/riscv/kernel/head.o
>
> -core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/
> +core-y += arch/riscv/errata/
> core-$(CONFIG_KVM) += arch/riscv/kvm/
>
> libs-y += arch/riscv/lib/
> diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
> index b8f8740a3e44..0ca1c5281a2d 100644
> --- a/arch/riscv/errata/Makefile
> +++ b/arch/riscv/errata/Makefile
> @@ -1,2 +1 @@
> -obj-y += alternative.o
> obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
> diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
> index 67406c376389..5dd8d03a13da 100644
> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -2,7 +2,7 @@
> #ifndef __ASM_ALTERNATIVE_MACROS_H
> #define __ASM_ALTERNATIVE_MACROS_H
>
> -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
> +#ifdef CONFIG_RISCV_ALTERNATIVE
>
> #ifdef __ASSEMBLY__
>
> @@ -76,7 +76,7 @@
>
> #endif /* __ASSEMBLY__ */
>
> -#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/
> +#else /* CONFIG_RISCV_ALTERNATIVE */
> #ifdef __ASSEMBLY__
>
> .macro __ALTERNATIVE_CFG old_c
> @@ -95,7 +95,8 @@
> __ALTERNATIVE_CFG(old_c)
>
> #endif /* __ASSEMBLY__ */
> -#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */
> +#endif /* CONFIG_RISCV_ALTERNATIVE */
> +
> /*
> * Usage:
> * ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k)
> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> index e625d3cafbed..7b42bcef0ecf 100644
> --- a/arch/riscv/include/asm/alternative.h
> +++ b/arch/riscv/include/asm/alternative.h
> @@ -12,6 +12,8 @@
>
> #ifndef __ASSEMBLY__
>
> +#ifdef CONFIG_RISCV_ALTERNATIVE
> +
> #include <linux/init.h>
> #include <linux/types.h>
> #include <linux/stddef.h>
> @@ -35,5 +37,11 @@ struct errata_checkfunc_id {
> void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> unsigned long archid, unsigned long impid);
>
> +#else /* CONFIG_RISCV_ALTERNATIVE */
> +
> +static inline void apply_boot_alternatives(void) { }
> +
> +#endif /* CONFIG_RISCV_ALTERNATIVE */
> +
> #endif
> #endif
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index 87adbe47bc15..0f8348ac30f1 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -18,6 +18,7 @@ extra-y += head.o
> extra-y += vmlinux.lds
>
> obj-y += soc.o
> +obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o
> obj-y += cpu.o
> obj-y += cpufeature.o
> obj-y += entry.o
> diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c
> similarity index 100%
> rename from arch/riscv/errata/alternative.c
> rename to arch/riscv/kernel/alternative.c
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 622f226454d5..a6d13dca1403 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running);
> void __init smp_prepare_boot_cpu(void)
> {
> init_cpu_topology();
> -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE
> apply_boot_alternatives();
> -#endif
> }
>
> void __init smp_prepare_cpus(unsigned int max_cpus)
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index fe92e119e6a3..efa693b325a1 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code,
> }
> }
>
> -#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE)
> +#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ALTERNATIVE)
> #define __trap_section __section(".xip.traps")
> #else
> #define __trap_section
> --
> 2.35.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Powered by blists - more mailing lists