linux-kernel - Re: [PATCH 1/3] media: st-mipid02: add support of pixel clock polarity

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 16 May 2022 12:12:21 +0200
From:   Benjamin Mugnier <benjamin.mugnier@...s.st.com>
To:     Hugues Fruchet <hugues.fruchet@...s.st.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Sylvain Petinot <sylvain.petinot@...s.st.com>
CC:     <linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Alain Volmat <alain.volmat@...s.st.com>
Subject: Re: [PATCH 1/3] media: st-mipid02: add support of pixel clock
 polarity

Hi Hugues,

Thank you for the patchset.

On 16/05/2022 11:19, Hugues Fruchet wrote:
> Add support of pixel clock polarity.
> 
> Signed-off-by: Hugues Fruchet <hugues.fruchet@...s.st.com>

Reviewed-by: Benjamin Mugnier <benjamin.mugnier@...s.st.com>

> ---
>  drivers/media/i2c/st-mipid02.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c
> index ef976d085d72..59b48026c752 100644
> --- a/drivers/media/i2c/st-mipid02.c
> +++ b/drivers/media/i2c/st-mipid02.c
> @@ -50,6 +50,7 @@
>  /* Bits definition for MIPID02_MODE_REG2 */
>  #define MODE_HSYNC_ACTIVE_HIGH				BIT(1)
>  #define MODE_VSYNC_ACTIVE_HIGH				BIT(2)
> +#define MODE_PCLK_SAMPLE_RISING				BIT(3)
>  /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
>  #define SELECTION_MANUAL_DATA				BIT(2)
>  #define SELECTION_MANUAL_WIDTH				BIT(3)
> @@ -494,6 +495,8 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
>  		bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
>  	if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
>  		bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
> +	if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
> +		bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
>  
>  	return 0;
>  }
>