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Message-ID: <21a16074-9179-f57b-a667-cccddcab6e24@microchip.com>
Date:   Tue, 17 May 2022 16:36:17 +0200
From:   Nicolas Ferre <nicolas.ferre@...rochip.com>
To:     Michael Walle <michael@...le.cc>,
        Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski@...onical.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Steen Hegelund <Steen.Hegelund@...rochip.com>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Gregory CLEMENT <gregory.clement@...tlin.com>,
        Paul Burton <paulburton@...nel.org>,
        "Quentin Schulz" <quentin.schulz@...tlin.com>,
        Antoine Tenart <atenart@...nel.org>,
        Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
CC:     "David S . Miller" <davem@...emloft.net>,
        <UNGLinuxDriver@...rochip.com>, <linux-gpio@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mips@...r.kernel.org>
Subject: Re: [PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes

On 19/03/2022 at 21:46, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The pinctrl device tree binding will be converted to YAML format. Rename
> the pin nodes so they end with "-pins" to match the schema.
> 
> Signed-off-by: Michael Walle <michael@...le.cc>

For the record:
Acked-by: Nicolas Ferre <nicolas.ferre@...rochip.com>

This patch was taken by Claudiu and sent in the PR targeting 5.19 
arm-soc tree via the at91-dt branch. It's currently in linux-next.

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
> index 3281af90ac6d..3c7e3a7d6f14 100644
> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>                  function = "fc3_b";
>          };
> 
> -       can0_b_pins:  can0_b_pins {
> +       can0_b_pins:  can0-b-pins {
>                  /* RX, TX */
>                  pins = "GPIO_35", "GPIO_36";
>                  function = "can0_b";
> --
> 2.30.2
> 


-- 
Nicolas Ferre

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