[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <6212bdfe-ecd2-3787-a2cb-b285318b102a@redhat.com>
Date: Tue, 17 May 2022 11:01:05 +0200
From: Paolo Bonzini <pbonzini@...hat.com>
To: "Yang, Weijiang" <weijiang.yang@...el.com>
Cc: "jmattson@...gle.com" <jmattson@...gle.com>,
"seanjc@...gle.com" <seanjc@...gle.com>,
"kan.liang@...ux.intel.com" <kan.liang@...ux.intel.com>,
"like.xu.linux@...il.com" <like.xu.linux@...il.com>,
"vkuznets@...hat.com" <vkuznets@...hat.com>,
"Wang, Wei W" <wei.w.wang@...el.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v11 14/16] KVM: x86/vmx: Flip Arch LBREn bit on guest
state change
On 5/17/22 10:56, Yang, Weijiang wrote:
>> I added more things to ease migration handling in SMM because: 1) qemu
>> checks LBREn before transfer Arch LBR MSRs.
I think it should always transfer them instead? There's time to post a
fixup patch.
>> 2) Perf event is created when
>> LBREn is being set. Two things are not certain: 1) IA32_LBR_CTL doesn't have
>> corresponding slot in SMRAM,not sure if we need to rely on it to transfer the MSR.
>> I chose 0x7f10 as the offset(CET takes 0x7f08) for storage, need you double check if
>> it's free or used.
0x7f10 sounds good.
> Hi, Paolo,
>
> I found there're some rebase conflicts between this series and your kvm
> queue branch due to PEBS patches, I can re-post a new version based on
> your queue branch if necessary.
Yes, please.
> Waiting for your comments on this patch...
I already commented that using bit 63 is not good, didn't I?
Paolo
Powered by blists - more mailing lists