linux-kernel - Re: [PATCH 2/3] phy: qcom-qmp: Add USB3 5NM QMP UNI registers

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Message-ID: <YoV1Lv02q2jB1ptd@yoga>
Date:   Wed, 18 May 2022 15:37:34 -0700
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Vinod Koul <vkoul@...nel.org>
Cc:     Kishon Vijay Abraham I <kishon@...com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] phy: qcom-qmp: Add USB3 5NM QMP UNI registers

On Tue 17 May 03:36 PDT 2022, Vinod Koul wrote:

> On 17-05-22, 16:01, Vinod Koul wrote:
> > On 13-05-22, 15:53, Bjorn Andersson wrote:
> > > Add all registers defines from qcom,usb3-5nm-qmp-uni.h of the msm-5.4
> > > kernel. Offsets are adjusted to be relative to each sub-block, as we
> > > describe the individual pieces in the upstream kernel and "5NM" are
> > > injected in the defines to not collide with existing constants.
> > > 
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> > > ---
> > >  .../phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h  | 617 ++++++++++++++++++
> > >  1 file changed, 617 insertions(+)
> > >  create mode 100644 drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > 
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > new file mode 100644
> > > index 000000000000..b912e50825f9
> > > --- /dev/null
> > > +++ b/drivers/phy/qualcomm/phy-qcom-usb3-5nm-qmp-uni.h
> > > @@ -0,0 +1,617 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> > 
> > should this be 2022 or add Linaro one for 2022..?
> > 
> > > + */
> > > +
> > > +#ifndef PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > > +#define PHY_QCOM_USB3_5NM_QMP_UNI_H_
> > > +
> > > +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */
> > > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL1			0x000
> > > +#define USB3_5NM_UNI_QSERDES_COM_ATB_SEL2			0x004
> > > +#define USB3_5NM_UNI_QSERDES_COM_FREQ_UPDATE			0x008
> > > +#define USB3_5NM_UNI_QSERDES_COM_BG_TIMER			0x00c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_EN_CENTER			0x010
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER1			0x014
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_ADJ_PER2			0x018
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER1			0x01c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_PER2			0x020
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x024
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x028
> 
> this seems to be QSERDES_V3_COM_* uptill now...
> 

Yes, some of these will be the same across several different versions of
QMP phys.

It takes me quite a bit of time trying to puzzle in missing entries in
the right place in the existing sets of defines. So the proposal here is
to use the generated files that exists for many of the QMP variants
downstream.

An example of this is that I got the USB combo phy for sc8280xp wrong,
because I couldn't copy paste the initialization sequence from the
downstream dts and we have mangled the names in the header file. So
either we just use the generated downstream file, or I will have to
spend a bunch of time trying to figure out which register(s) I got
wrong.

> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0		0x02c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x030
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x034
> > > +#define USB3_5NM_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1		0x038
> > > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV			0x03c
> > > +#define USB3_5NM_UNI_QSERDES_COM_POST_DIV_MUX			0x040
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x044
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_ENABLE1			0x048
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYS_CLK_CTRL			0x04c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE		0x050
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_EN				0x054
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_IVCO			0x058
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IETRIM			0x05c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_IPTRIM			0x060
> > > +#define USB3_5NM_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x064
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x068
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE0		0x06c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_EP_DIV_MODE1		0x070
> > > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE0			0x074
> > > +#define USB3_5NM_UNI_QSERDES_COM_CP_CTRL_MODE1			0x078
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE0		0x07c
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_RCTRL_MODE1		0x080
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE0		0x084
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CCTRL_MODE1		0x088
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_CNTRL			0x08c
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x090
> > > +#define USB3_5NM_UNI_QSERDES_COM_SYSCLK_EN_SEL			0x094
> > > +#define USB3_5NM_UNI_QSERDES_COM_CML_SYSCLK_SEL			0x098
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL			0x09c
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESETSM_CNTRL2			0x0a0
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_EN			0x0a4
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP_CFG			0x0a8
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE0		0x0ac
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE0		0x0b0
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP1_MODE1		0x0b4
> > > +#define USB3_5NM_UNI_QSERDES_COM_LOCK_CMP2_MODE1		0x0b8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE0		0x0bc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE0		0x0c0
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MODE1		0x0c4
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEC_START_MSB_MODE1		0x0c8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0		0x0cc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0		0x0d0
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0		0x0d4
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1		0x0d8
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1		0x0dc
> > > +#define USB3_5NM_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1		0x0e0
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_INITVAL		0x0e4
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_EN			0x0e8
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x0ec
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0f0
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x0f4
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x0f8
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0		0x0fc
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1		0x100
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x104
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_CTRL			0x108
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAP			0x10c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE0		0x110
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE0		0x114
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE1_MODE1		0x118
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE2_MODE1		0x11c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL1		0x120
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_INITVAL2		0x124
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL1		0x128
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MINVAL2		0x12c
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1		0x130
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2		0x134
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER1		0x138
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_TUNE_TIMER2		0x13c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_STATUS			0x140
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESET_SM_STATUS		0x144
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESTRIM_CODE_STATUS		0x148
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS		0x14c
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS		0x150
> > > +#define USB3_5NM_UNI_QSERDES_COM_CLK_SELECT			0x154
> > > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_SEL			0x158
> > > +#define USB3_5NM_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL		0x15c
> > > +#define USB3_5NM_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x160
> > > +#define USB3_5NM_UNI_QSERDES_COM_PLL_ANALOG			0x164
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE0		0x168
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORECLK_DIV_MODE1		0x16c
> > > +#define USB3_5NM_UNI_QSERDES_COM_SW_RESET			0x170
> > > +#define USB3_5NM_UNI_QSERDES_COM_CORE_CLK_EN			0x174
> > > +#define USB3_5NM_UNI_QSERDES_COM_C_READY_STATUS			0x178
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_CONFIG			0x17c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_RATE_OVERRIDE		0x180
> > > +#define USB3_5NM_UNI_QSERDES_COM_SVS_MODE_CLK_SEL		0x184
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS0			0x188
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS1			0x18c
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS2			0x190
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS3			0x194
> > > +#define USB3_5NM_UNI_QSERDES_COM_DEBUG_BUS_SEL			0x198
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MISC1			0x19c
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE			0x1a0
> > > +#define USB3_5NM_UNI_QSERDES_COM_CMN_MODE_CONTD			0x1a4
> > > +#define USB3_5NM_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL		0x1a8
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
> > > +#define USB3_5NM_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
> > > +#define USB3_5NM_UNI_QSERDES_COM_RESERVED_1			0x1c0
> > > +#define USB3_5NM_UNI_QSERDES_COM_MODE_OPERATION_STATUS		0x1c4
> 
> these are offset now...
> 

Not sure I see what you mean?

> Any reason why this should be 5NM and not use the VX convention we
> have...?
> 

The downstream file is named "5nm" and not V5, so this was simply an
attempt to reduce the effort spent maintaining these defines.

Regards,
Bjorn