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Message-ID: <20220518095735.GB430350@leoy-ThinkPad-X240s>
Date: Wed, 18 May 2022 17:57:35 +0800
From: Leo Yan <leo.yan@...aro.org>
To: James Clark <james.clark@....com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
broonie@...nel.org, acme@...nel.org, german.gomez@....com,
mathieu.poirier@...aro.org, john.garry@...wei.com,
Will Deacon <will@...nel.org>,
Mike Leach <mike.leach@...aro.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register
On Wed, May 18, 2022 at 10:44:57AM +0100, James Clark wrote:
[...]
> >> + if (getauxval(AT_HWCAP) & HWCAP_SVE)
> >> + attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG);
> >> +
> >> + /*
> >> + * Check if the pmu supports perf extended regs, before
> >> + * returning the register mask to sample.
> >> + */
> >> + if (attr.sample_regs_user != PERF_REGS_MASK) {
> >> + event_attr_init(&attr);
> >> + fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> >> + if (fd != -1) {
> >> + close(fd);
> >> + return attr.sample_regs_user;
> >> + }
> >> + }
> >
> > Just curious, since we can know SVE is supported from reading
> > auxiliary value, can we directly return the register mask as below?
> >
> > PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG);
>
> I was trying to cover the case where the system supports SVE, but
> the kernel doesn't have my changes to add the VG register yet.
>
> Technically I could just attempt to open the event without checking
> for SVE first and see if it works or not. But I preferred to be
> explicit so it's obvious why we're doing that.
Understand; LGTM.
Reviewed-by: Leo Yan <leo.yan@...aro.org>
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