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Message-ID: <20220518115129.908787-2-claudiu.beznea@microchip.com>
Date: Wed, 18 May 2022 14:51:28 +0300
From: Claudiu Beznea <claudiu.beznea@...rochip.com>
To: <srinivas.kandagatla@...aro.org>, <robh+dt@...nel.org>,
<krzk+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: [PATCH v3 1/2] dt-bindings: microchip-otpc: document Microchip OTPC
Document Microchip OTP controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
.../nvmem/microchip,sama7g5-otpc.yaml | 50 +++++++++++++++++++
.../nvmem/microchip,sama7g5-otpc.h | 12 +++++
2 files changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
create mode 040000 include/dt-bindings/nvmem
create mode 100644 include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
new file mode 100644
index 000000000000..c3c96fd0baac
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip SAMA7G5 OTP Controller (OTPC)
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea@...rochip.com>
+
+description: |
+ OTP controller drives a NVMEM memory where system specific data
+ (e.g. calibration data for analog cells, hardware configuration
+ settings, chip identifiers) or user specific data could be stored.
+
+allOf:
+ - $ref: "nvmem.yaml#"
+
+properties:
+ compatible:
+ items:
+ - const: microchip,sama7g5-otpc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
+
+ otpc: efuse@...00000 {
+ compatible = "microchip,sama7g5-otpc", "syscon";
+ reg = <0xe8c00000 0xec>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ temperature_calib: calib@1 {
+ reg = <OTP_PKT(1) 76>;
+ };
+ };
+
+...
diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
new file mode 100644
index 000000000000..f570b23165a2
--- /dev/null
+++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
+#define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H
+
+/*
+ * Need to have it as a multiple of 4 as NVMEM memory is registered with
+ * stride = 4.
+ */
+#define OTP_PKT(id) ((id) * 4)
+
+#endif
--
2.34.1
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