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Message-Id: <20220518132350.35762-1-alim.akhtar@samsung.com>
Date: Wed, 18 May 2022 18:53:50 +0530
From: Alim Akhtar <alim.akhtar@...sung.com>
To: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: devicetree@...r.kernel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-fsd@...la.com,
Alim Akhtar <alim.akhtar@...sung.com>
Subject: [PATCH] arm64: dts: fsd: Add cpu cache information
Add CPU caches information so that the same is available to
userspace via sysfs. This SoC has 48/32 KB I/D cache for
each CPU cores and 4MB of L2 cache.
Signed-off-by: Alim Akhtar <alim.akhtar@...sung.com>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 91 ++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 7ad634533104..36480a9b34c4 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -93,6 +93,13 @@ cpucl0_0: cpu@0 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_1: cpu@1 {
@@ -102,6 +109,13 @@ cpucl0_1: cpu@1 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_2: cpu@2 {
@@ -111,6 +125,13 @@ cpucl0_2: cpu@2 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl0_3: cpu@3 {
@@ -119,6 +140,13 @@ cpucl0_3: cpu@3 {
reg = <0x0 0x003>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
/* Cluster 1 */
@@ -129,6 +157,13 @@ cpucl1_0: cpu@100 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_1: cpu@101 {
@@ -138,6 +173,13 @@ cpucl1_1: cpu@101 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_2: cpu@102 {
@@ -147,6 +189,13 @@ cpucl1_2: cpu@102 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl1_3: cpu@103 {
@@ -156,6 +205,13 @@ cpucl1_3: cpu@103 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
/* Cluster 2 */
@@ -166,6 +222,13 @@ cpucl2_0: cpu@200 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_1: cpu@201 {
@@ -175,6 +238,13 @@ cpucl2_1: cpu@201 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_2: cpu@202 {
@@ -184,6 +254,13 @@ cpucl2_2: cpu@202 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
};
cpucl2_3: cpu@203 {
@@ -193,6 +270,20 @@ cpucl2_3: cpu@203 {
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&cpucl_l2>;
+ };
+
+ cpucl_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x400000>;
+ cache-line-size = <64>;
+ cache-sets = <4096>;
};
idle-states {
--
2.25.1
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