linux-kernel - Re: [PATCH] perf regs x86: Fix arch__intr_reg

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Message-ID: <CAP-5=fWKmR-bDbiocSAd4qkrf7_ge+e1_gYLjQqRfGyc8FP4Sw@mail.gmail.com>
Date:   Wed, 18 May 2022 21:38:20 -0700
From:   Ian Rogers <irogers@...gle.com>
To:     kan.liang@...ux.intel.com
Cc:     acme@...nel.org, mingo@...hat.com, namhyung@...nel.org,
        jolsa@...nel.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, peterz@...radead.org,
        zhengjun.xing@...ux.intel.com, Ammy Yi <ammy.yi@...el.com>
Subject: Re: [PATCH] perf regs x86: Fix arch__intr_reg_mask() for the hybrid platform

On Wed, May 18, 2022 at 7:52 AM <kan.liang@...ux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@...ux.intel.com>
>
> The X86 specific arch__intr_reg_mask() is to check whether the kernel
> and hardware can collect XMM registers. But it doesn't work on some
> hybrid platform.
>
> Without the patch on ADL-N,
>
> $perf record -I?
> available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10
> R11 R12 R13 R14 R15
>
> The config of the test event doesn't contain the PMU information. The
> kernel may fail to initialize it on the correct hybrid PMU and return
> the wrong non-supported information.
>
> Add the PMU information into the config for the hybrid platform. The
> same register set is supported among different hybrid PMUs. Checking
> the first available one is good enough.
>
> With the patch on ADL-N,
>
> $perf record -I?
> available registers: AX BX CX DX SI DI BP SP IP FLAGS CS SS R8 R9 R10
> R11 R12 R13 R14 R15 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9
> XMM10 XMM11 XMM12 XMM13 XMM14 XMM15
>
> Fixes: 6466ec14aaf4 ("perf regs x86: Add X86 specific arch__intr_reg_mask()")
> Reported-by: Ammy Yi <ammy.yi@...el.com>
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>

Acked-by: Ian Rogers <irogers@...gle.com>

> ---
>  tools/perf/arch/x86/util/perf_regs.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
> index 207c56805c55..0ed177991ad0 100644
> --- a/tools/perf/arch/x86/util/perf_regs.c
> +++ b/tools/perf/arch/x86/util/perf_regs.c
> @@ -9,6 +9,8 @@
>  #include "../../../util/perf_regs.h"
>  #include "../../../util/debug.h"
>  #include "../../../util/event.h"
> +#include "../../../util/pmu.h"
> +#include "../../../util/pmu-hybrid.h"
>
>  const struct sample_reg sample_reg_masks[] = {
>         SMPL_REG(AX, PERF_REG_X86_AX),
> @@ -284,12 +286,22 @@ uint64_t arch__intr_reg_mask(void)
>                 .disabled               = 1,
>                 .exclude_kernel         = 1,
>         };
> +       struct perf_pmu *pmu;

nit: this could have smaller scope if just be declared in the if-block.

Thanks,
Ian

>         int fd;
>         /*
>          * In an unnamed union, init it here to build on older gcc versions
>          */
>         attr.sample_period = 1;
>
> +       if (perf_pmu__has_hybrid()) {
> +               /*
> +                * The same register set is supported among different hybrid PMUs.
> +                * Only check the first available one.
> +                */
> +               pmu = list_first_entry(&perf_pmu__hybrid_pmus, typeof(*pmu), hybrid_list);
> +               attr.config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT;
> +       }
> +
>         event_attr_init(&attr);
>
>         fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
> --
> 2.35.1
>