linux-kernel - Re: [PATCH v15 07/14] KVM: VMX: Emulate reads and writes to CET MSRs

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Message-ID: <908bc121-ceb8-e296-3397-643733016ecc@intel.com>
Date:   Thu, 19 May 2022 16:49:22 +0800
From:   "Yang, Weijiang" <weijiang.yang@...el.com>
To:     Sean Christopherson <seanjc@...gle.com>,
        John Allen <john.allen@....com>
Cc:     pbonzini@...hat.com, jmattson@...gle.com, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, yu.c.zhang@...ux.intel.com
Subject: Re: [PATCH v15 07/14] KVM: VMX: Emulate reads and writes to CET MSRs


On 5/19/2022 12:16 AM, Sean Christopherson wrote:
> On Wed, May 18, 2022, John Allen wrote:
>> On Wed, Feb 03, 2021 at 07:34:14PM +0800, Yang Weijiang wrote:
>>> +	case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP:
>>> +		if (!cet_is_ssp_msr_accessible(vcpu, msr_info))
>>> +			return 1;
>>> +		if ((data & GENMASK(2, 0)) || is_noncanonical_address(data, vcpu))
>> Sorry to revive this old thread. I'm working on the corresponding SVM
>> bits for shadow stack and I noticed the above check. Why isn't this
>> GENMASK(1, 0)? The *SSP MSRs should be a 4-byte aligned canonical
>> address meaning that just bits 1 and 0 should always be zero. I was
>> looking through the previous versions of the set and found that this
>> changed between versions 11 and 12, but I don't see any discussion
>> related to this on the list.
> Huh.  I'm not entirely sure what to make of the SDM's wording:
>
>    The linear address written must be aligned to 8 bytes and bits 2:0 must be 0
>    (hardware requires bits 1:0 to be 0).
>
> Looking at the rest of the CET stuff, I believe requiring 8-byte alignment is
> correct, and that the "hardware requires" blurb is trying to call out that the
> SSP stored in hardware will always be 4-byte aligned but not necessarily 8-byte
> aligned in order to play nice with 32-bit/compatibility mode.  But "base" addresses
> that come from software, e.g. via MSRs and whatnot, must always be 8-byte aligned.
Thanks Sean, I cannot agree more ;-)