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Message-ID: <1359379ef34da760f108b075ac138ab082caa3ba.1652954372.git.sandipan.das@amd.com>
Date: Thu, 19 May 2022 15:33:34 +0530
From: Sandipan Das <sandipan.das@....com>
To: <linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
<x86@...nel.org>
CC: <peterz@...radead.org>, <bp@...en8.de>, <acme@...nel.org>,
<namhyung@...nel.org>, <jolsa@...nel.org>, <tglx@...utronix.de>,
<mingo@...hat.com>, <pbonzini@...hat.com>, <jmattson@...gle.com>,
<like.xu.linux@...il.com>, <eranian@...gle.com>,
<ananth.narayan@....com>, <ravi.bangoria@....com>,
<santosh.shukla@....com>, <sandipan.das@....com>
Subject: [PATCH 5/5] perf/x86/amd/uncore: Add PerfMonV2 RDPMC assignments
The current RDPMC assignment scheme maps four DF PMCs and
six L3 PMCs from index 6 to 15.
If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, there may be additional DF counters available
which are mapped starting from index 16 i.e. just after
the L3 counters. Update the RDPMC assignments accordingly.
Signed-off-by: Sandipan Das <sandipan.das@....com>
---
arch/x86/events/amd/uncore.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index ff4238eff087..d568afc705d2 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -158,6 +158,16 @@ static int amd_uncore_add(struct perf_event *event, int flags)
hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;
hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+ /*
+ * The first four DF counters are accessible via RDPMC index 6 to 9
+ * followed by the L3 counters from index 10 to 15. For processors
+ * with more than four DF counters, the DF RDPMC assignments become
+ * discontiguous as the additional counters are accessible starting
+ * from index 16.
+ */
+ if (is_nb_event(event) && hwc->idx >= NUM_COUNTERS_NB)
+ hwc->event_base_rdpmc += NUM_COUNTERS_L3;
+
if (flags & PERF_EF_START)
amd_uncore_start(event, PERF_EF_RELOAD);
--
2.34.1
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