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Date: Sat, 21 May 2022 16:54:48 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Rob Herring <robh@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Mike Leach <mike.leach@...aro.org>,
Leo Yan <leo.yan@...aro.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/2] dt-bindings: arm: Convert CoreSight bindings to DT
schema
On 20/05/2022 23:44, Rob Herring wrote:
> Each CoreSight component has slightly different requirements and
> nothing applies to every component, so each CoreSight component has its
> own schema document.
>
(...)
> + const: arm,coresight-dynamic-funnel
> + required:
> + - compatible
> +
> +allOf:
> + - $ref: /schemas/arm/primecell.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: arm,coresight-dynamic-funnel
> + - const: arm,primecell
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: apb_pclk
> + - const: atclk
> +
> + in-ports:
> + $ref: /schemas/graph.yaml#/properties/ports
Shouldn't this be with unevaluatedProperties:false?
> +
> + patternProperties:
> + '^port(@[0-7])?$':
> + description: Input connections from CoreSight Trace bus
> + $ref: /schemas/graph.yaml#/properties/port
> +
> + out-ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + additionalProperties: false
> +
> + properties:
> + port:
> + description: Output connection to CoreSight Trace bus
> + $ref: /schemas/graph.yaml#/properties/port
> +
(...)
> +title: Arm CoreSight Static Trace Bus Replicator
> +
> +maintainers:
> + - Mathieu Poirier <mathieu.poirier@...aro.org>
> + - Mike Leach <mike.leach@...aro.org>
> + - Leo Yan <leo.yan@...aro.org>
> + - Suzuki K Poulose <suzuki.poulose@....com>
> +
> +description: |
> + CoreSight components are compliant with the ARM CoreSight architecture
> + specification and can be connected in various topologies to suit a particular
> + SoCs tracing needs. These trace components can generally be classified as
> + sinks, links and sources. Trace data produced by one or more sources flows
> + through the intermediate links connecting the source to the currently selected
> + sink.
> +
> + The Coresight replicator splits a single trace stream into two trace streams
> + for systems that have more than one trace sink component.
> +
> +properties:
> + compatible:
> + const: arm,coresight-static-replicator
> +
> + in-ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + additionalProperties: false
> +
> + properties:
> + port:
> + description: Input connection from CoreSight Trace bus
> + $ref: /schemas/graph.yaml#/properties/port
> +
> + out-ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + patternProperties:
> + '^port@[01]$':
> + description: Output connections to CoreSight Trace bus
> + $ref: /schemas/graph.yaml#/properties/port
> +
Same question.
(...)
> +title: Arm CoreSight Trace Memory Controller
> +
> +maintainers:
> + - Mathieu Poirier <mathieu.poirier@...aro.org>
> + - Mike Leach <mike.leach@...aro.org>
> + - Leo Yan <leo.yan@...aro.org>
> + - Suzuki K Poulose <suzuki.poulose@....com>
> +
> +description: |
> + CoreSight components are compliant with the ARM CoreSight architecture
> + specification and can be connected in various topologies to suit a particular
> + SoCs tracing needs. These trace components can generally be classified as
> + sinks, links and sources. Trace data produced by one or more sources flows
> + through the intermediate links connecting the source to the currently selected
> + sink.
> +
> + Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
> + FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
> + mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
> +
> +# Need a custom select here or 'arm,primecell' will match on lots of nodes
> +select:
> + properties:
> + compatible:
> + contains:
> + const: arm,coresight-tmc
> + required:
> + - compatible
> +
> +allOf:
> + - $ref: /schemas/arm/primecell.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: arm,coresight-tmc
> + - const: arm,primecell
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: apb_pclk
> + - const: atclk
> +
> + arm,buffer-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + deprecated: true
> + description:
> + Size of contiguous buffer space for TMC ETR (embedded trace router). The
> + buffer size can be configured dynamically via buffer_size property in
> + sysfs instead.
> +
> + arm,scatter-gather:
> + type: boolean
> + description:
> + Indicates that the TMC-ETR can safely use the SG mode on this system.
> +
> + arm,max-burst-size:
> + description:
> + The maximum burst size initiated by TMC on the AXI master interface. The
> + burst size can be in the range [0..15], the setting supports one data
> + transfer per burst up to a maximum of 16 data transfers per burst.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maximum: 15
> +
> +
Just one blank line
Best regards,
Krzysztof
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