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Message-Id: <20220522155046.260146-13-tmaimon77@gmail.com>
Date: Sun, 22 May 2022 18:50:39 +0300
From: Tomer Maimon <tmaimon77@...il.com>
To: avifishman70@...il.com, tali.perry1@...il.com, joel@....id.au,
venture@...gle.com, yuenn@...gle.com, benjaminfair@...gle.com,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
gregkh@...uxfoundation.org, daniel.lezcano@...aro.org,
tglx@...utronix.de, wim@...ux-watchdog.org, linux@...ck-us.net,
catalin.marinas@....com, will@...nel.org, arnd@...db.de,
olof@...om.net, jirislaby@...nel.org, shawnguo@...nel.org,
bjorn.andersson@...aro.org, geert+renesas@...der.be,
marcel.ziswiler@...adex.com, vkoul@...nel.org,
biju.das.jz@...renesas.com, nobuhiro1.iwamatsu@...hiba.co.jp,
robert.hancock@...ian.com, j.neuschaefer@....net, lkundrak@...sk
Cc: soc@...nel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-serial@...r.kernel.org, linux-watchdog@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Tomer Maimon <tmaimon77@...il.com>
Subject: [PATCH v1 12/19] reset: npcm: Add NPCM8XX support
Updated the NPCM reset driver to add
support for Nuvoton BMC NPCM8XX SoC.
As part of adding NPCM8XX support
- Add NPCM8XX specific compatible string.
- Add NPCM8XX USB reset.
- Some of the Reset Id and number of resets are
different from NPCM7XX.
Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
---
drivers/reset/reset-npcm.c | 157 ++++++++++++++++++++++++++++++-------
1 file changed, 130 insertions(+), 27 deletions(-)
diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c
index 0c963b21eddc..8d82a45dd580 100644
--- a/drivers/reset/reset-npcm.c
+++ b/drivers/reset/reset-npcm.c
@@ -17,13 +17,20 @@
/* NPCM7xx GCR registers */
#define NPCM_MDLR_OFFSET 0x7C
-#define NPCM_MDLR_USBD0 BIT(9)
-#define NPCM_MDLR_USBD1 BIT(8)
-#define NPCM_MDLR_USBD2_4 BIT(21)
-#define NPCM_MDLR_USBD5_9 BIT(22)
+#define NPCM7XX_MDLR_USBD0 BIT(9)
+#define NPCM7XX_MDLR_USBD1 BIT(8)
+#define NPCM7XX_MDLR_USBD2_4 BIT(21)
+#define NPCM7XX_MDLR_USBD5_9 BIT(22)
+
+/* NPCM8xx MDLR bits */
+#define NPCM8XX_MDLR_USBD0_3 BIT(9)
+#define NPCM8XX_MDLR_USBD4_7 BIT(22)
+#define NPCM8XX_MDLR_USBD8 BIT(24)
+#define NPCM8XX_MDLR_USBD9 BIT(21)
#define NPCM_USB1PHYCTL_OFFSET 0x140
#define NPCM_USB2PHYCTL_OFFSET 0x144
+#define NPCM_USB3PHYCTL_OFFSET 0x148
#define NPCM_USBXPHYCTL_RS BIT(28)
/* NPCM7xx Reset registers */
@@ -49,12 +56,17 @@
#define NPCM_IPSRST3_USBPHY1 BIT(24)
#define NPCM_IPSRST3_USBPHY2 BIT(25)
+#define NPCM_IPSRST4 0x74
+#define NPCM_IPSRST4_USBPHY3 BIT(25)
+#define NPCM_IPSRST4_USB_HOST2 BIT(31)
+
#define NPCM_RC_RESETS_PER_REG 32
#define NPCM_MASK_RESETS GENMASK(4, 0)
struct npcm_rc_data {
struct reset_controller_dev rcdev;
struct notifier_block restart_nb;
+ struct regmap *gcr_regmap;
u32 sw_reset_number;
void __iomem *base;
spinlock_t lock;
@@ -124,7 +136,7 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
offset = reset_spec->args[0];
if (offset != NPCM_IPSRST1 && offset != NPCM_IPSRST2 &&
- offset != NPCM_IPSRST3) {
+ offset != NPCM_IPSRST3 && offset != NPCM_IPSRST4) {
dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
return -EINVAL;
}
@@ -139,39 +151,28 @@ static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
static const struct of_device_id npcm_rc_match[] = {
{ .compatible = "nuvoton,npcm750-reset"},
+ { .compatible = "nuvoton,npcm845-reset"},
{ }
};
-/*
- * The following procedure should be observed in USB PHY, USB device and
- * USB host initialization at BMC boot
- */
-static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
+static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
{
u32 mdlr, iprst1, iprst2, iprst3;
- struct device *dev = &pdev->dev;
- struct regmap *gcr_regmap;
u32 ipsrst1_bits = 0;
u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
u32 ipsrst3_bits = 0;
- gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
- if (IS_ERR(gcr_regmap)) {
- dev_err(&pdev->dev, "Failed to find gcr syscon");
- return PTR_ERR(gcr_regmap);
- }
-
/* checking which USB device is enabled */
- regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
- if (!(mdlr & NPCM_MDLR_USBD0))
+ regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
+ if (!(mdlr & NPCM7XX_MDLR_USBD0))
ipsrst3_bits |= NPCM_IPSRST3_USBD0;
- if (!(mdlr & NPCM_MDLR_USBD1))
+ if (!(mdlr & NPCM7XX_MDLR_USBD1))
ipsrst1_bits |= NPCM_IPSRST1_USBD1;
- if (!(mdlr & NPCM_MDLR_USBD2_4))
+ if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
NPCM_IPSRST1_USBD3 |
NPCM_IPSRST1_USBD4);
- if (!(mdlr & NPCM_MDLR_USBD0)) {
+ if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
NPCM_IPSRST1_USBD6);
ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
@@ -194,9 +195,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
writel(iprst3, rc->base + NPCM_IPSRST3);
/* clear USB PHY RS bit */
- regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
NPCM_USBXPHYCTL_RS, 0);
- regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
NPCM_USBXPHYCTL_RS, 0);
/* deassert reset USB PHY */
@@ -206,9 +207,9 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
udelay(50);
/* set USB PHY RS bit */
- regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
- regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
/* deassert reset USB devices*/
@@ -219,6 +220,108 @@ static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
writel(iprst1, rc->base + NPCM_IPSRST1);
writel(iprst2, rc->base + NPCM_IPSRST2);
writel(iprst3, rc->base + NPCM_IPSRST3);
+}
+
+static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
+{
+ u32 mdlr, iprst1, iprst2, iprst3, iprst4;
+ u32 ipsrst1_bits = 0;
+ u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
+ u32 ipsrst3_bits = 0;
+ u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
+
+ /* checking which USB device is enabled */
+ regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
+ if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
+ ipsrst3_bits |= NPCM_IPSRST3_USBD0;
+ ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
+ NPCM_IPSRST1_USBD2 |
+ NPCM_IPSRST1_USBD3);
+ }
+ if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
+ ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
+ NPCM_IPSRST1_USBD5 |
+ NPCM_IPSRST1_USBD6);
+ ipsrst3_bits |= NPCM_IPSRST3_USBD7;
+ }
+
+ if (!(mdlr & NPCM8XX_MDLR_USBD8))
+ ipsrst3_bits |= NPCM_IPSRST3_USBD8;
+ if (!(mdlr & NPCM8XX_MDLR_USBD9))
+ ipsrst3_bits |= NPCM_IPSRST3_USBD9;
+
+ /* assert reset USB PHY and USB devices */
+ iprst1 = readl(rc->base + NPCM_IPSRST1);
+ iprst2 = readl(rc->base + NPCM_IPSRST2);
+ iprst3 = readl(rc->base + NPCM_IPSRST3);
+ iprst4 = readl(rc->base + NPCM_IPSRST4);
+
+ iprst1 |= ipsrst1_bits;
+ iprst2 |= ipsrst2_bits;
+ iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
+ NPCM_IPSRST3_USBPHY2);
+ iprst2 |= ipsrst4_bits;
+
+ writel(iprst1, rc->base + NPCM_IPSRST1);
+ writel(iprst2, rc->base + NPCM_IPSRST2);
+ writel(iprst3, rc->base + NPCM_IPSRST3);
+ writel(iprst4, rc->base + NPCM_IPSRST4);
+
+ /* clear USB PHY RS bit */
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, 0);
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, 0);
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, 0);
+
+ /* deassert reset USB PHY */
+ iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
+ writel(iprst3, rc->base + NPCM_IPSRST3);
+ iprst4 &= ~NPCM_IPSRST4_USBPHY3;
+ writel(iprst4, rc->base + NPCM_IPSRST4);
+
+ /* set USB PHY RS bit */
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+ regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
+ NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
+
+ /* deassert reset USB devices*/
+ iprst1 &= ~ipsrst1_bits;
+ iprst2 &= ~ipsrst2_bits;
+ iprst3 &= ~ipsrst3_bits;
+ iprst4 &= ~ipsrst4_bits;
+
+ writel(iprst1, rc->base + NPCM_IPSRST1);
+ writel(iprst2, rc->base + NPCM_IPSRST2);
+ writel(iprst3, rc->base + NPCM_IPSRST3);
+ writel(iprst4, rc->base + NPCM_IPSRST4);
+}
+
+/*
+ * The following procedure should be observed in USB PHY, USB device and
+ * USB host initialization at BMC boot
+ */
+static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+
+ rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
+ if (IS_ERR(rc->gcr_regmap)) {
+ dev_err(&pdev->dev, "Failed to find gcr syscon");
+ return PTR_ERR(rc->gcr_regmap);
+ }
+
+ if (of_device_is_compatible(np, "nuvoton,npcm750-reset"))
+ npcm_usb_reset_npcm7xx(rc);
+ else if (of_device_is_compatible(np, "nuvoton,npcm845-reset"))
+ npcm_usb_reset_npcm8xx(rc);
+ else
+ return -ENODEV;
return 0;
}
--
2.33.0
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