linux-kernel - [PATCH v4 3/3] x86: Fix comment for X86_FEATURE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <2333afe4e6acb52999c941ad20713d1b445223bd.1653324016.git-series.wyes.karny@amd.com>
Date:   Mon, 23 May 2022 22:25:51 +0530
From:   Wyes Karny <wyes.karny@....com>
To:     <linux-kernel@...r.kernel.org>
CC:     <Lewis.Carroll@....com>, <Mario.Limonciello@....com>,
        <gautham.shenoy@....com>, <Ananth.Narayan@....com>,
        <bharata@....com>, <len.brown@...el.com>, <x86@...nel.org>,
        <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
        <dave.hansen@...ux.intel.com>, <hpa@...or.com>,
        <peterz@...radead.org>, <chang.seok.bae@...el.com>,
        <keescook@...omium.org>, <metze@...ba.org>,
        <zhengqi.arch@...edance.com>, <mark.rutland@....com>,
        <rui.zhang@...el.com>, <puwen@...on.cn>,
        <rafael.j.wysocki@...el.com>, <andrew.cooper3@...rix.com>,
        <jing2.liu@...el.com>, <jmattson@...gle.com>,
        <pawan.kumar.gupta@...ux.intel.com>
Subject: [PATCH v4 3/3] x86: Fix comment for X86_FEATURE_ZEN

The feature X86_FEATURE_ZEN implies that the CPU based on Zen
microarchitecture. Call this out explicitly in the comment.

Signed-off-by: Wyes Karny <wyes.karny@....com>
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 73e643ae94b6..6141457cda38 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -219,7 +219,7 @@
 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
+#define X86_FEATURE_ZEN			(7*32+28) /* "" CPU based on Zen microarchitecture */
 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
-- 
git-series 0.9.1