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Message-ID: <39132f3173df651ea0e2d7ea399008b9ba8d1892.camel@mediatek.com>
Date: Mon, 23 May 2022 13:11:01 +0800
From: Rex-BC Chen <rex-bc.chen@...iatek.com>
To: "Nícolas F. R. A. Prado" <nfraprado@...labora.com>
CC: "mturquette@...libre.com" <mturquette@...libre.com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
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<angelogioacchino.delregno@...labora.com>,
Chun-Jie Chen (陳浚桀)
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<linux-mediatek@...ts.infradead.org>,
Project_Global_Chrome_Upstream_Group
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Subject: Re: [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells
property for MT8195
On Fri, 2022-05-20 at 23:30 +0800, Nícolas F. R. A. Prado wrote:
> Hi Rex,
>
> On Thu, May 19, 2022 at 08:55:24PM +0800, Rex-BC Chen wrote:
> > We will use mediatek clock reset as infracfg_ao reset instead of
> > ti-syscon. To support this, remove property of ti reset and add
> > property of #reset-cells for mediatek clock reset.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@...labora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
> > 1 file changed, 1 insertion(+), 12 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index b57e620c2c72..8e5ac11b19f1 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -10,7 +10,6 @@
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> > -#include <dt-bindings/reset/ti-syscon.h>
> >
> > / {
> > compatible = "mediatek,mt8195";
> > @@ -295,17 +294,7 @@
> > compatible = "mediatek,mt8195-infracfg_ao",
> > "syscon", "simple-mfd";
>
> I believe the 'simple-mfd' compatible was added only to make the
> reset-controller subnode probe (at least this was the case for
> mt8192), so it
> might make sense to drop it here as well.
>
> Thanks,
> Nícolas
>
Hello Nícolas,
ok, I will drop 'simple-mfd' in next version.
BRs,
Rex
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > -
> > - infracfg_rst: reset-controller {
> > - compatible = "ti,syscon-reset";
> > - #reset-cells = <1>;
> > - ti,reset-bits = <
> > - 0x140 18 0x144 18 0 0
> > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> > - 0x120 0 0x124 0 0 0
> > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> > - 0x730 10 0x734 10 0 0
> > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> > - 0x150 5 0x154 5 0 0
> > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> > - >;
> > - };
> > + #reset-cells = <1>;
> > };
> >
> > pericfg: syscon@...03000 {
> > --
> > 2.18.0
> >
> >
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