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Message-ID: <20220523093346.28493-16-rex-bc.chen@mediatek.com>
Date:   Mon, 23 May 2022 17:33:42 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <matthias.bgg@...il.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>
CC:     <p.zabel@...gutronix.de>,
        <angelogioacchino.delregno@...labora.com>,
        <nfraprado@...labora.com>, <chun-jie.chen@...iatek.com>,
        <wenst@...omium.org>, <runyang.chen@...iatek.com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: [RESEND v8 15/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8192

To support reset of infra, we add property of #reset-cells.

Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: NĂ­colas F. R. A. Prado <nfraprado@...labora.com>
Tested-by: NĂ­colas F. R. A. Prado <nfraprado@...labora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 733aec2e7f77..13ba5fee4afa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -271,6 +271,7 @@
 			compatible = "mediatek,mt8192-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		pericfg: syscon@...03000 {
-- 
2.18.0

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