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Message-Id: <20220523150334.1758649-1-jiaqing.zhao@linux.intel.com>
Date: Mon, 23 May 2022 23:03:35 +0800
From: Jiaqing Zhao <jiaqing.zhao@...ux.intel.com>
To: linux-mtd@...ts.infradead.org,
Tudor Ambarus <tudor.ambarus@...rochip.com>,
Pratyush Yadav <p.yadav@...com>,
Michael Walle <michael@...le.cc>
Cc: linux-kernel@...r.kernel.org,
Jiaqing Zhao <jiaqing.zhao@...ux.intel.com>
Subject: [PATCH v3] mtd: spi-nor: macronix: Add support for mx66l2g45g
Macronix mx66l2g45g is a 3V, 2Gbit (256MB) NOR flash that supports
x1, x2, and x4 operation modes.
Tested read/write/erase with Aspeed AST2600 BMC SoC operating in x2
mode at 50MHz, using Aspeed spi-mem driver.
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@...ux.intel.com>
---
drivers/mtd/spi-nor/macronix.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index d81a4cb2812b..33d02a01b381 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -95,6 +95,8 @@ static const struct flash_info macronix_nor_parts[] = {
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
+ // TODO: Use SNOR_ID3() for "mx66l2g45g"
+ { "mx66l2g45g", INFO(0xc2201c, 0, 0, 0) PARSE_SFDP },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048)
NO_SFDP_FLAGS(SPI_NOR_QUAD_READ) },
{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096)
--
2.34.1
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