Message-ID: <CAP6Zq1iPw7QzzdHV77s08-MLKrtC+VCdnWxUjb9WTXpf822f8g@mail.gmail.com>
Date:   Tue, 24 May 2022 10:26:11 +0300
From:   Tomer Maimon <tmaimon77@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Geert Uytterhoeven <geert@...ux-m68k.org>,
        Avi Fishman <avifishman70@...il.com>,
        Tali Perry <tali.perry1@...il.com>,
        Joel Stanley <joel@....id.au>,
        Patrick Venture <venture@...gle.com>,
        Nancy Yuen <yuenn@...gle.com>,
        Benjamin Fair <benjaminfair@...gle.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Greg KH <gregkh@...uxfoundation.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Arnd Bergmann <arnd@...db.de>,
        Olof Johansson <olof@...om.net>,
        Jiri Slaby <jirislaby@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Björn Andersson <bjorn.andersson@...aro.org>,
        Marcel Ziswiler <marcel.ziswiler@...adex.com>,
        Vinod Koul <vkoul@...nel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>,
        Robert Hancock <robert.hancock@...ian.com>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        Lubomir Rintel <lkundrak@...sk>, arm-soc <soc@...nel.org>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        Linux Watchdog Mailing List <linux-watchdog@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX

Hi Krzysztof and Geert,

Appreciate your comments!

We are using the same binding method in the NPCM7XX that it is
upstreamed a few years ago.
https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

In the Reset NPCM driver we check the reset spec arguments that are
using the correct register offset and BIT.
https://github.com/torvalds/linux/blob/master/drivers/reset/reset-npcm.c#L125

One more thing,
Sorry about the mail format, I am using Gmail and now I am moving it
to plain text mode. hope it will help.
Any other suggestion to set the Gmail to work with the Linux community
will help alot

On Mon, 23 May 2022 at 18:23, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 23/05/2022 17:11, Geert Uytterhoeven wrote:
> > Hi Krzysztof,
> >
> > On Mon, May 23, 2022 at 4:26 PM Krzysztof Kozlowski
> > <krzysztof.kozlowski@...aro.org> wrote:
> >> On 23/05/2022 16:22, Geert Uytterhoeven wrote:
> >>> On Mon, May 23, 2022 at 4:03 PM Tomer Maimon <tmaimon77@...il.com> wrote:
> >>>> On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> wrote:
> >>>>> On 22/05/2022 17:50, Tomer Maimon wrote:
> >>>>>> Add binding document and device tree binding
> >>>>>> constants for Nuvoton BMC NPCM8XX reset controller.
> >>>>>>
> >>>>>> Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
> >>>
> >>>>>> --- /dev/null
> >>>>>> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> >>>>>> @@ -0,0 +1,124 @@
> >>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>> +// Copyright (c) 2022 Nuvoton Technology corporation.
> >>>>>> +
> >>>>>> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> >>>>>> +
> >>>>>> +#define NPCM8XX_RESET_IPSRST1                0x20
> >>>>>> +#define NPCM8XX_RESET_IPSRST2                0x24
> >>>>>> +#define NPCM8XX_RESET_IPSRST3                0x34
> >>>>>> +#define NPCM8XX_RESET_IPSRST4                0x74
> >>>>>
> >>>>> What are these? All IDs should be incremental, decimal and start from 0.
> >>>>
> >>>> Register offset, we use the same method in NPCM7xx. please refer
> >>>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
> >>>>
> >>>> and the driver asserts the reset according to the reset include definitions
> >>>
> >>> So if they're easy to look up the values, you could do without the
> >>> definitions? Cfr. the interrupts properties in .dtsi files, where we
> >>> typically just use the hardcoded numbers.
> >>>
> >>> If you do decide to keep them, a comment explaining their origins
> >>> would be useful.
Will do it in the next patch.
> >>>
> >>>>>> +
> >>>>>> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> >>>>>> +#define NPCM8XX_RESET_GDMA0          3
> >>>>>
> >>>>> IDs start from 0 and do not have holes.
> >>>>
> >>>> This represents the reset BIT in the reset register.
> >>>
> >>> Likewise, I think it's a good idea to document that in a comment, cfr.
> >>> https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/power/r8a7795-sysc.h#L8
> >>
> >> Renesas is also doing it not correct (just like many others). The
> >> bindings are not for register bits or offsets. Such data can be DTS but
> >> not part of bindings.
> >
> > I think you are taking a too-extremist standpoint.
> > The two extremes are:
> >   1. Numbers correspond to hardware numbers, and are easy to look up
> >     in the hardware documentation (e.g. GIC SPI interrupt numbers).
> >      => Use the hardcoded numbers in DTS.
>
> And such numbers (like GIC_SPI interrupt numbers) do not go to bindings.
> They go to DTS only.
>
> >   2. Numbers do not correspond to hardware numbers, so we had to
> >      invent our own definitions and numbers, usually loosely
> >      based on some table in the hardware documentation.
> >      The driver will have to look up the numbers in a data
> >      structure, to know how to program the hardware.
> >      The numbers become part of the DT ABI, and cannot be changed
> >      (header file is append-only).
> >      => Use the binding definitions in DTS.
>
> Correct.
>
> However this patch is some mixture of both approaches.
>
> The same pointed by Arnd:
> https://lore.kernel.org/linux-devicetree/CAK8P3a0fDJQvGLEtG0fxLkG08Fh9V7LEMPsx4AaS+2Ldo_xWxw@mail.gmail.com/
>
> > We are taking the middle ground: there is a one-to-one relation between
> > numbers and hardware numbers that can be looked up in or derived from
> > the hardware documentation, but the conversion is non-trivial (for the
> > casual human reviewer), or the documentation refers to names instead
> > of numbers in most sections (e.g. named power domains). Then why not
> > let the numbers match some feature in the hardware (e.g. register
> > offset or register bit)?
>
> Because you are embedding the device programming model into the
> bindings. It's the same as having properties:
> "vendor,value-for-register-xxx"
>
> We do not create bindings to describe programming model but hardware.
> Using the values from programming model is fragile and ties the bindings
> to that one programming model. Programming model can change, e.g. by
> mistake, but bindings should stay independent.
>
> >
> >> Imagine now you made mistake in this register
> >> offset and hardware uses slightly different value. What now? Change
> >> bindings? No. Bindings hold here ID, the abstraction, and ID stays fixed.
> >
> > I see no difference here with using the wrong interrupt number in an
> > interrupts property in DTS.  What do we do in that case? Fix the DTS.
>
> Yes, fix the DTS. DTS are not the bindings. You can fix the DTS. You
> cannot fix the bindings because you affect both driver and DTS.
>
> >
> > BTW, are you aware of any driver that transforms interrupt numbers
> > obtained from DTS, because the DTS used the wrong number?
>
> Again, what do the DTS has here at all? The interrupt numbers are also
> not included in the bindings, so what does it prove?
>
> Best regards,
> Krzysztof

Best regards,

Tomer

Powered by blists - more mailing lists