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Date: Tue, 24 May 2022 17:25:53 +0200
From: Alexandre Bailon <abailon@...libre.com>
To: rafael@...nel.org, rui.zhang@...el.com, daniel.lezcano@...aro.org,
amitk@...nel.org
Cc: linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
khilman@...libre.com, mka@...omium.org, robh+dt@...nel.org,
krzk+dt@...nel.org, matthias.bgg@...il.com, p.zabel@...gutronix.de,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, james.lo@...iatek.com,
fan.chen@...iatek.com, louis.yu@...iatek.com,
rex-bc.chen@...iatek.com, Tinghan Shen <tinghan.shen@...iatek.com>,
Ben Tseng <ben.tseng@...iatek.com>,
Alexandre Bailon <abailon@...libre.com>
Subject: [PATCH v7 6/6] arm64: dts: mt8195: Add thermal zone
From: Tinghan Shen <tinghan.shen@...iatek.com>
This adds the thermal zone for the mt8195.
Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
Signed-off-by: Ben Tseng <ben.tseng@...iatek.com>
Signed-off-by: Alexandre Bailon <abailon@...libre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 104 +++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 51443e83d906..8421cf35ae03 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -812,6 +813,21 @@ spi0: spi@...0a000 {
status = "disabled";
};
+ lvts: lvts@...0b000 {
+ compatible = "mediatek,mt8195-lvts";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100b000 0 0x1000>,
+ <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>,
+ <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+
+ nvmem-cells = <&lvts_e_data1 &lvts_e_data2>;
+ nvmem-cell-names = "e_data1","e_data2";
+ };
+
spi1: spi@...10000 {
compatible = "mediatek,mt8195-spi",
"mediatek,mt6765-spi";
@@ -1616,4 +1632,92 @@ vencsys_core1: clock-controller@...00000 {
#clock-cells = <1>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu-big1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 0>;
+ };
+ cpu-big2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 1>;
+ };
+ cpu-big3-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 2>;
+ };
+ cpu-big4-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 3>;
+ };
+ cpu-little1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 4>;
+ };
+ cpu-little2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 5>;
+ };
+ cpu-little3-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 6>;
+ };
+ cpu-little4-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 7>;
+ };
+ vpu1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 8>;
+ };
+ vpu2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 9>;
+ };
+ gpu1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 10>;
+ };
+ gpu2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 11>;
+ };
+ vdec-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 12>;
+ };
+ img-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 13>;
+ };
+ infra-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 14>;
+ };
+ cam1-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 15>;
+ };
+ cam2-thermal {
+ polling-delay = <0>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&lvts 16>;
+ };
+ };
};
--
2.35.1
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