[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20220525185853.695931-3-paul.kocialkowski@bootlin.com>
Date: Wed, 25 May 2022 20:58:48 +0200
From: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org
Cc: Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Frank Rowand <frowand.list@...il.com>,
Maxime Ripard <mripard@...nel.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Paul Kocialkowski <paul.kocialkowski@...tlin.com>
Subject: [PATCH v4 2/7] clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header
In order to declare a mbus node for the v3s, expose its associated
clocks to the public header.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 4 ----
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++--
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
index 108eeeedcbf7..8ed4eff86ca1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
@@ -39,14 +39,10 @@
/* The first bunch of module clocks are exported */
-#define CLK_DRAM 58
-
/* All the DRAM gates are exported */
/* Some more module clocks are exported */
-#define CLK_MBUS 72
-
/* And the GPU module clock is exported */
#define CLK_PLL_DDR1 74
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index 014ac6123d17..4231f23bc53b 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -87,7 +87,7 @@
#define CLK_SPI0 55
#define CLK_USB_PHY0 56
#define CLK_USB_OHCI0 57
-
+#define CLK_DRAM 58
#define CLK_DRAM_VE 59
#define CLK_DRAM_CSI 60
#define CLK_DRAM_EHCI 61
@@ -101,7 +101,7 @@
#define CLK_VE 69
#define CLK_AC_DIG 70
#define CLK_AVS 71
-
+#define CLK_MBUS 72
#define CLK_MIPI_CSI 73
/* Clocks not available on V3s */
--
2.36.1
Powered by blists - more mailing lists