lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Wed, 25 May 2022 11:21:33 +0800
From:   <yf.wang@...iatek.com>
To:     <miles.chen@...iatek.com>
CC:     <Libo.Kang@...iatek.com>, <Yong.Wu@...iatek.com>,
        <iommu@...ts.linux-foundation.org>, <isaacm@...eaurora.org>,
        <joro@...tes.org>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>, <matthias.bgg@...il.com>,
        <ning.li@...iatek.com>, <quic_c_gdjako@...cinc.com>,
        <robin.murphy@....com>, <sven@...npeter.dev>, <will@...nel.org>,
        <wsd_upstream@...iatek.com>, <yf.wang@...iatek.com>
Subject: Re: [PATCH v5 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit

On Thu, 2022-05-19 at 14:27 +0800, Miles Chen wrote:
> Hi Yunfei,
> 
> > The calling to kmem_cache_alloc for level 2 pgtable allocation may
> > run
> > in atomic context, and it fails sometimes when DMA32 zone runs out
> > of
> > memory.
> > 
> > Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
> > so add a quirk to allow the PA of pgtables support up to bit35.
> > 
> > Signed-off-by: Ning Li <ning.li@...iatek.com>
> > Signed-off-by: Yunfei Wang <yf.wang@...iatek.com>
> > ---
> >  drivers/iommu/io-pgtable-arm-v7s.c | 56 ++++++++++++++++++++++--
> > ------
> >  include/linux/io-pgtable.h         | 15 +++++---
> >  2 files changed, 52 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-
> > pgtable-arm-v7s.c
> 
> ...snip...
> 
> > +     gfp_t gfp_l1 = __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA;
> >       struct io_pgtable_cfg *cfg = &data->iop.cfg;
> >       struct device *dev = cfg->iommu_dev;
> >       phys_addr_t phys;
> > @@ -241,9 +251,11 @@ static void *__arm_v7s_alloc_table(int lvl,
> > gfp_t gfp,
> >       size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
> >       void *table = NULL;
> > 
> > +     if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
> > +             gfp_l1 = __GFP_ZERO;
> 
> __GFP_ZERO is an action modifier, if we do not want
> ARM_V7S_TABLE_GFP_DMA (GFP_DMA/GFP_DMA32), use gfp_l1 = (GFP_KERNEL |
> __GFP_ZERO)
> 

Hi Miles,
Thanks for the suggestion, we will update it in the next version.

Thanks,
Yunfei.

> > +
> >       if (lvl == 1)
> > -             table = (void *)__get_free_pages(
> > -                     __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA,
> > get_order(size));
> > +             table = (void *)__get_free_pages(gfp_l1,
> > get_order(size));
> >       else if (lvl == 2)
> >               table = kmem_cache_zalloc(data->l2_tables, gfp);
> > 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ