linux-kernel - [PATCH 2/3] iommu: bindings: Add binding documentation for Toshiba Visconti5 IOMMU device

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Message-Id: <20220525013147.2215355-3-nobuhiro1.iwamatsu@toshiba.co.jp>
Date:   Wed, 25 May 2022 10:31:46 +0900
From:   Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
To:     Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     yuji2.ishikawa@...hiba.co.jp, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
        Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
Subject: [PATCH 2/3] iommu: bindings: Add binding documentation for Toshiba Visconti5 IOMMU device

Add documentation for the binding of Toshiba Visconti5 SoC's IOMMU.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
---
 .../bindings/iommu/toshiba,visconti-atu.yaml  | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml

diff --git a/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml
new file mode 100644
index 000000000000..af8d6688fa70
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/toshiba,visconti-atu.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/toshiba,visconti-atu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba ARM SoC Visconti5 IOMMU (ATU)
+
+maintainers:
+  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
+
+description: |+
+  IOMMU (ATU) driver can bse used for Visconti5's multimedia IPs, such as
+  DCNN (Deep Convolutional Neural Network), VIIF(Video Input), VOIF(Video
+  output), and others.
+
+properties:
+  compatible:
+    const: toshiba,visconti-atu
+
+  reg:
+    maxItems: 1
+
+  "#iommu-cells":
+    const: 0
+
+  toshiba,max-entry:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The size of entry for address
+    enum:
+      - 16
+      - 32
+
+  toshiba,reserved-entry:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: The reserve number of entry address.
+    default: 0
+    minimum: 0
+    maximum: 32
+
+required:
+  - compatible
+  - reg
+  - "#iommu-cells"
+  - toshiba,max-entry
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        atu_affine0: iommu@...0f000 {
+            compatible = "toshiba,visconti-atu";
+            reg = <0 0x1400F000 0 0x1000>;
+            toshiba,max-entry = <16>;
+            toshiba,reserved-entry = <1>;
+            #iommu-cells = <0>;
+        };
+    };
-- 
2.36.0