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Message-Id: <20220525151106.2176147-1-sunilvl@ventanamicro.com>
Date: Wed, 25 May 2022 20:41:01 +0530
From: Sunil V L <sunilvl@...tanamicro.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ard Biesheuvel <ardb@...nel.org>,
Marc Zyngier <maz@...nel.org>,
Atish Patra <atishp@...osinc.com>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Anup Patel <apatel@...tanamicro.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-efi@...r.kernel.org, Sunil V L <sunil.vl@...il.com>,
Sunil V L <sunilvl@...tanamicro.com>
Subject: [PATCH 0/5] Support for 64bit hartid on RV64 platforms
The hartid can be a 64bit value on RV64 platforms. This series updates
the code so that 64bit hartid can be supported on RV64 platforms.
Sunil V L (5):
riscv: cpu_ops_sbi: Support for 64bit hartid
riscv: cpu_ops_spinwait: Support for 64bit hartid
riscv: smp: Support for 64bit hartid
riscv: cpu: Support for 64bit hartid
riscv/efi_stub: Support for 64bit boot-hartid
arch/riscv/include/asm/processor.h | 4 ++--
arch/riscv/include/asm/smp.h | 4 ++--
arch/riscv/kernel/cpu.c | 26 +++++++++++++----------
arch/riscv/kernel/cpu_ops_sbi.c | 4 ++--
arch/riscv/kernel/cpu_ops_spinwait.c | 2 +-
arch/riscv/kernel/cpufeature.c | 6 ++++--
arch/riscv/kernel/smp.c | 4 ++--
arch/riscv/kernel/smpboot.c | 9 ++++----
drivers/clocksource/timer-riscv.c | 15 +++++++------
drivers/firmware/efi/libstub/riscv-stub.c | 12 ++++++++---
drivers/irqchip/irq-riscv-intc.c | 7 +++---
drivers/irqchip/irq-sifive-plic.c | 7 +++---
12 files changed, 58 insertions(+), 42 deletions(-)
--
2.25.1
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