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Date: Wed, 25 May 2022 20:41:03 +0530 From: Sunil V L <sunilvl@...tanamicro.com> To: Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Ard Biesheuvel <ardb@...nel.org>, Marc Zyngier <maz@...nel.org>, Atish Patra <atishp@...osinc.com>, Heinrich Schuchardt <heinrich.schuchardt@...onical.com>, Anup Patel <apatel@...tanamicro.com> Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-efi@...r.kernel.org, Sunil V L <sunil.vl@...il.com>, Sunil V L <sunilvl@...tanamicro.com> Subject: [PATCH 2/5] riscv: cpu_ops_spinwait: Support for 64bit hartid The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L <sunilvl@...tanamicro.com> --- arch/riscv/kernel/cpu_ops_spinwait.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_ops_spinwait.c index 346847f6c41c..51ac07514a62 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".data"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); /* * The hartid must be less than NR_CPUS to avoid out-of-bound access -- 2.25.1
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