linux-kernel - Re: [PATCH 04/13] perf/x86/amd: Support PERF_SAMPLE_WEIGHT using IBS OP

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Date:   Thu, 26 May 2022 17:44:54 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Stephane Eranian <eranian@...gle.com>
Cc:     peterz@...radead.org, acme@...nel.org, jolsa@...nel.org,
        namhyung@...nel.org, irogers@...gle.com, jmario@...hat.com,
        leo.yan@...aro.org, alisaidi@...zon.com, ak@...ux.intel.com,
        kan.liang@...ux.intel.com, dave.hansen@...ux.intel.com,
        hpa@...or.com, mingo@...hat.com, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, tglx@...utronix.de,
        bp@...en8.de, x86@...nel.org, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, sandipan.das@....com,
        ananth.narayan@....com, kim.phillips@....com,
        santosh.shukla@....com, Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 04/13] perf/x86/amd: Support PERF_SAMPLE_WEIGHT using IBS
 OP_DATA3[IbsDcMissLat]

On 25-May-22 6:28 PM, Stephane Eranian wrote:
> On Wed, May 25, 2022 at 12:42 PM Ravi Bangoria <ravi.bangoria@....com> wrote:
>>
>> IBS Op data3 provides data cache miss latency which can be passed as
>> sample->weight along with perf_mem_data_src. Note that sample->weight
>> will be populated only when PERF_SAMPLE_DATA_SRC is also set, although
>> both sample types are independent.
>>
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
>> ---
>>  arch/x86/events/amd/ibs.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
>> index 6626caeed6a1..5a6e278713f4 100644
>> --- a/arch/x86/events/amd/ibs.c
>> +++ b/arch/x86/events/amd/ibs.c
>> @@ -738,6 +738,12 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, u64 op_data2,
>>                 return;
>>         }
>>
>> +       /* Load latency (Data cache miss latency) */
>> +       if (data_src->mem_op == PERF_MEM_OP_LOAD &&
>> +           event->attr.sample_type & PERF_SAMPLE_WEIGHT) {
>> +               data->weight.full = (op_data3 & IBS_DC_MISS_LAT_MASK) >> IBS_DC_MISS_LAT_SHIFT;
>> +       }
>> +
> I think here you also need to handle the WEIGHT_STRUCT case and put
> the cache miss latency in the right
> field. This IBS field covers the cache line movement and not the whole
> instruction latency which is the tag to ret field.
> In the case of WEIGHT_STRUCT you need to fill out the two fields.

Yeah, will do. Thanks for pointing it.

-Ravi