lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220527083556.18864-2-r-ravikumar@ti.com>
Date:   Fri, 27 May 2022 14:05:54 +0530
From:   Rahul T R <r-ravikumar@...com>
To:     <robh+dt@...nel.org>, <nm@...com>, <vigneshr@...com>,
        <kishon@...com>, <krzysztof.kozlowski+dt@...aro.org>
CC:     <lee.jones@...aro.org>, <rogerq@...nel.org>,
        <devicetree@...r.kernel.org>, <kristo@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <s-anna@...com>,
        Rahul T R <r-ravikumar@...com>
Subject: [PATCH 1/3] dt-bindings: mfd: ti,j721e-system-controller: Add clock property

Add a pattern property for clock, also update the example with
a clock node

Signed-off-by: Rahul T R <r-ravikumar@...com>
---
 .../bindings/mfd/ti,j721e-system-controller.yaml     | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index fa86691ebf16..e774a7f0bb08 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -48,6 +48,12 @@ patternProperties:
     description:
       This is the SERDES lane control mux.
 
+  "^clock@[0-9a-f]+$":
+    type: object
+    $ref: ../clock/ti,am654-ehrpwm-tbclk.yaml#
+    description:
+      This is TI syscon gate clk.
+
 required:
   - compatible
   - reg
@@ -79,5 +85,11 @@ examples:
                 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
                 /* SERDES4 lane0/1/2/3 select */
         };
+
+        ehrpwm_tbclk: clock@...0 {
+                compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+                reg = <0x4140 0x18>;
+                #clock-cells = <1>;
+        };
     };
 ...
-- 
2.17.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ