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Message-ID: <4d7f39188b76d509909b0c6274ad2bd89723b8d4.camel@nxp.com>
Date: Tue, 31 May 2022 09:45:52 +0800
From: Liu Ying <victor.liu@....com>
To: Peng Fan <peng.fan@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Cc: Abel Vesa <abel.vesa@....com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>
Subject: Re: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table
properly in ->recalc_rate()
Hi Peng,
On Mon, 2022-05-30 at 17:08 +0800, Peng Fan wrote:
> > Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate
> > table properly
> > in ->recalc_rate()
> >
> > > Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate
> > > table
> > > properly in
> > > ->recalc_rate()
> > >
> > > The PLL parameters in rate table should be directly compared with
> > > those read from PLL registers instead of the cooked ones.
> > >
> > > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> > > Cc: Abel Vesa <abel.vesa@....com>
> > > Cc: Michael Turquette <mturquette@...libre.com>
> > > Cc: Stephen Boyd <sboyd@...nel.org>
> > > Cc: Shawn Guo <shawnguo@...nel.org>
> > > Cc: Sascha Hauer <s.hauer@...gutronix.de>
> > > Cc: Pengutronix Kernel Team <kernel@...gutronix.de>
> > > Cc: Fabio Estevam <festevam@...il.com>
> > > Cc: NXP Linux Team <linux-imx@....com>
> > > Cc: Peng Fan <peng.fan@....com>
> > > Signed-off-by: Liu Ying <victor.liu@....com>
> >
> > Reviewed-by: Peng Fan <peng.fan@....com>
> >
> > > ---
> > > drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
> > > 1 file changed, 13 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-fracn-gppll.c
> > > b/drivers/clk/imx/clk-fracn-gppll.c
> > > index 71c102d950ab..762b07dd5a6d 100644
> > > --- a/drivers/clk/imx/clk-fracn-gppll.c
> > > +++ b/drivers/clk/imx/clk-fracn-gppll.c
> > > @@ -131,18 +131,7 @@ static unsigned long
> > > clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> > > mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
> > >
> > > rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
> > > - rdiv = rdiv + 1;
> > > odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
> > > - switch (odiv) {
> > > - case 0:
> > > - odiv = 2;
> > > - break;
> > > - case 1:
> > > - odiv = 3;
> > > - break;
> > > - default:
> > > - break;
> > > - }
> > >
> > > /*
> > > * Sometimes, the recalculated rate has deviation due to @@
> > > -160,6
> > > +149,19 @@ static unsigned long
> > > clk_fracn_gppll_recalc_rate(struct
> > > +clk_hw
> > > *hw, unsigned lon
> > > if (rate)
> > > return (unsigned long)rate;
> > >
> > > + rdiv = rdiv + 1;
>
> After check more:
> According to doc, needs add a check here:
> if (!rdiv)
> rdiv = rdiv + 1;
This new check is not something this patch tries to deal with.
Maybe, you may send a separate patch to add the check.
Regards,
Liu Ying
>
> Regards,
> Peng.
> > > +
> > > + switch (odiv) {
> > > + case 0:
> > > + odiv = 2;
> > > + break;
> > > + case 1:
> > > + odiv = 3;
> > > + break;
> > > + default:
> > > + break;
> > > + }
> > > +
> > > /* Fvco = Fref * (MFI + MFN / MFD) */
> > > fvco = fvco * mfi * mfd + fvco * mfn;
> > > do_div(fvco, mfd * rdiv * odiv);
> > > --
> > > 2.25.1
>
>
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