linux-kernel - Re: [PATCH 2/3] net: ethernet: ti: am65-cpsw: Add support for QSGMII mode

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Message-ID: <YpYBBp8Io116bBwM@shell.armlinux.org.uk>
Date:   Tue, 31 May 2022 12:50:30 +0100
From:   "Russell King (Oracle)" <linux@...linux.org.uk>
To:     Siddharth Vadapalli <s-vadapalli@...com>
Cc:     davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
        pabeni@...hat.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, vladimir.oltean@....com,
        grygorii.strashko@...com, vigneshr@...com, nsekhar@...com,
        netdev@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, kishon@...com
Subject: Re: [PATCH 2/3] net: ethernet: ti: am65-cpsw: Add support for QSGMII
 mode

On Tue, May 31, 2022 at 05:00:57PM +0530, Siddharth Vadapalli wrote:
>  static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
>  				      const struct phylink_link_state *state)
>  {
> -	/* Currently not used */
> +	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
> +							  phylink_config);
> +	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
> +
> +	if (state->interface == PHY_INTERFACE_MODE_QSGMII)
> +		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
> +		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

What about writing this register when the interface mode isn't QSGMII?

-- 
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