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Message-ID: <089a240d-7419-527c-9d99-261920bc654e@amd.com>
Date: Wed, 1 Jun 2022 09:55:12 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: Kim Phillips <kim.phillips@....com>
Cc: peterz@...radead.org, acme@...nel.org, jolsa@...nel.org,
namhyung@...nel.org, eranian@...gle.com, irogers@...gle.com,
jmario@...hat.com, leo.yan@...aro.org, alisaidi@...zon.com,
ak@...ux.intel.com, kan.liang@...ux.intel.com,
dave.hansen@...ux.intel.com, hpa@...or.com, mingo@...hat.com,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
tglx@...utronix.de, bp@...en8.de, x86@...nel.org,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
sandipan.das@....com, ananth.narayan@....com,
santosh.shukla@....com, Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit
definitions
Hi Kim,
On 26-May-22 8:38 PM, Kim Phillips wrote:
> On 5/25/22 4:39 AM, Ravi Bangoria wrote:
>
> Hi Ravi,
>
>> AMD IBS OP_DATA2 and OP_DATA3 provides detail about tagged load/store
>> ops. Add definitions for these registers into header file. In addition
>> to those, IBS_OP_DATA2 DataSrc provides detail about location of the
>> data being accessed from by load ops. Define macros for legacy and
>> extended DataSrc values.
>>
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
>> ---
>> arch/x86/include/asm/amd-ibs.h | 76 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 76 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
>> index aabdbb5ab920..22184fe20cf0 100644
>> --- a/arch/x86/include/asm/amd-ibs.h
>> +++ b/arch/x86/include/asm/amd-ibs.h
>> @@ -6,6 +6,82 @@
>> #include <asm/msr-index.h>
>> +/* IBS_OP_DATA2 Bits */
>> +#define IBS_DATA_SRC_HI_SHIFT 6
>> +#define IBS_DATA_SRC_HI_MASK (0x3ULL << IBS_DATA_SRC_HI_SHIFT)
>
> Is there a reason we're not using the existing bitfield
> definitions? E.g., data_src_hi for the case above.
Yes, we might be able to use those. Thanks for pointing.
- Ravi
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