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Message-ID: <20220601112201.15510-16-tinghan.shen@mediatek.com>
Date: Wed, 1 Jun 2022 19:22:01 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: Bjorn Andersson <bjorn.andersson@...aro.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Lee Jones <lee.jones@...aro.org>,
Benson Leung <bleung@...omium.org>,
Guenter Roeck <groeck@...omium.org>,
Daisuke Nojiri <dnojiri@...omium.org>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
"Dustin L. Howett" <dustin@...ett.net>,
Tzung-Bi Shih <tzungbi@...nel.org>,
Tinghan Shen <tinghan.shen@...iatek.com>,
"Gustavo A. R. Silva" <gustavoars@...nel.org>,
Prashant Malani <pmalani@...omium.org>,
"Enric Balletbo i Serra" <enric.balletbo@...labora.com>,
Brian Norris <briannorris@...omium.org>
CC: <linux-remoteproc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <chrome-platform@...ts.linux.dev>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
<weishunc@...gle.com>
Subject: [PATCH v1 15/15] mfd: cros_ec: Add SCP core 1 as a new CrOS EC MCU
MT8195 System Companion Processors(SCP) is a dual-core RISC-V MCU.
Add a new cros feature id to represent the SCP 2nd core.
The 1st core is referred to as 'core 0', and the 2nd core is referred
to as 'core 1'.
Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
---
drivers/mfd/cros_ec_dev.c | 5 +++++
include/linux/platform_data/cros_ec_commands.h | 2 ++
include/linux/platform_data/cros_ec_proto.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c
index 596731caf407..07cc31d92edc 100644
--- a/drivers/mfd/cros_ec_dev.c
+++ b/drivers/mfd/cros_ec_dev.c
@@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = {
.name = CROS_EC_DEV_SCP_NAME,
.desc = "System Control Processor",
},
+ {
+ .id = EC_FEATURE_SCP_C1,
+ .name = CROS_EC_DEV_SCP_C1_NAME,
+ .desc = "System Control Processor 2nd Core",
+ },
{
.id = EC_FEATURE_TOUCHPAD,
.name = CROS_EC_DEV_TP_NAME,
diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h
index 8cfa8cfca77e..9fbf1c5eb8d3 100644
--- a/include/linux/platform_data/cros_ec_commands.h
+++ b/include/linux/platform_data/cros_ec_commands.h
@@ -1300,6 +1300,8 @@ enum ec_feature_code {
* mux.
*/
EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
+ /* The MCU is a System Companion Processor (SCP) 2nd Core. */
+ EC_FEATURE_SCP_C1 = 45,
};
#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h
index 138fd912c808..da06dc7cf1cb 100644
--- a/include/linux/platform_data/cros_ec_proto.h
+++ b/include/linux/platform_data/cros_ec_proto.h
@@ -19,6 +19,7 @@
#define CROS_EC_DEV_ISH_NAME "cros_ish"
#define CROS_EC_DEV_PD_NAME "cros_pd"
#define CROS_EC_DEV_SCP_NAME "cros_scp"
+#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1"
#define CROS_EC_DEV_TP_NAME "cros_tp"
/*
--
2.18.0
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