linux-kernel - RE: arch/riscv: SV48 patch series questions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e99af0ab0a264aadb77d949c4b73fd57@EXMBX161.cuchost.com>
Date:   Thu, 2 Jun 2022 05:43:42 +0000
From:   Leyfoon Tan <leyfoon.tan@...rfivetech.com>
To:     Palmer Dabbelt <palmer@...belt.com>
CC:     "alexandre.ghiti@...onical.com" <alexandre.ghiti@...onical.com>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: arch/riscv: SV48 patch series questions



> -----Original Message-----
> From: Palmer Dabbelt <palmer@...belt.com>
> Sent: Thursday, 2 June, 2022 11:44 AM
> To: Leyfoon Tan <leyfoon.tan@...rfivetech.com>
> Cc: alexandre.ghiti@...onical.com; linux-riscv@...ts.infradead.org; linux-
> kernel@...r.kernel.org
> Subject: Re: arch/riscv: SV48 patch series questions
> 
> On Fri, 27 May 2022 02:37:34 PDT (-0700), leyfoon.tan@...rfivetech.com
> wrote:
> > Hi Palmer
> >
> > Alex's "Introduce sv48 support without relocatable kernel" patch series in
> [1] was partially merged to Linux v5.17. But there are 4 patches are not
> merged (Patch-10 to 13).
> >
> > May I know what is the plan for these patches? Will them merged to next
> v5.19 merging window? Or do you expect any changes for these patches or
> Alex needs resend with rebase to latest kernel version?
> 
> I just saw this as I was digging up Alex's old email to reply to, all but #13 are
> now on for-next.
> 
> > Note, we would like to use the Patch-13 in this series.
> 
> Is your use case a CPU errata?  If so I think we should just go ahead and add
> that errata via the existing errata mechanism.  If you've got some other use
> case, do you mind elaborating?  From that other thread it sounds like a
> command-line argument is the way to go for folks who want to turn this off
> more dynamically, but happy to hear if you've got something different in
> mind.
It is not CPU errata. 
RISC-V cpu can have sv39, sv48 or even sv57. If it is a heterogenous system, cpu cores in the system might have different sv. Eg: one cpu can be sv39 and another core is sv48.
In this case, auto detection is not work. So, Patch-13 can help in this use case.

> 
> > Patches not merged:
> > [v3,10/13] riscv: Improve virtual kernel memory layout dump [v3,11/13]
> > Documentation: riscv: Add sv48 description to VM layout [v3,12/13]
> > riscv: Initialize thread pointer before calling C functions [v3,13/13]
> > riscv: Allow user to downgrade to sv39 when hw supports sv48 if !KASAN
> >
> > [1]:
> > https://patchwork.kernel.org/project/linux-riscv/cover/20211206104657.
> > 433304-1-alexandre.ghiti@...onical.com/
> >

Thanks.

Regards
Ley Foon