linux-kernel - Re: [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs

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Message-ID: <e970f47d462b0cca9bc6107843721b6b0aabd73a.camel@mediatek.com>
Date:   Thu, 2 Jun 2022 14:18:29 +0800
From:   Yong Wu <yong.wu@...iatek.com>
To:     Fabien Parent <fparent@...libre.com>
CC:     Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
        "Matthias Brugger" <matthias.bgg@...il.com>,
        <iommu@...ts.linux-foundation.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded
 port IDs

Hi Fabien,

Thanks for very much for this patch.

Retitle to iommu/mediatek: Xxx

On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote:
> Until now the port ID was always encoded as a 5-bit data. On MT8365,
> the port ID is encoded as a 6-bit data. This requires to rework the
> macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order
> to support 5-bit and 6-bit encoded port IDs.
> 
> Signed-off-by: Fabien Parent <fparent@...libre.com>
> ---
>  drivers/iommu/mtk_iommu.c | 17 +++++++++++++----
>  drivers/iommu/mtk_iommu.h |  1 +
>  2 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 6fd75a60abd6..b692347d8d56 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -103,8 +103,10 @@
>  #define REG_MMU1_INT_ID				0x154
>  #define F_MMU_INT_ID_COMM_ID(a)			(((a) >> 9) &
> 0x7)
>  #define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)
> -#define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) &
> 0x7)
> -#define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) &
> 0x1f)
> +#define F_MMU_INT_ID_LARB_ID(a, port_width)	\
> +				((a) >> ((port_width + 2) & 0x7))
> +#define F_MMU_INT_ID_PORT_ID(a, port_width)	\
> +				(((a) >> 2) & GENMASK(port_width - 1,
> 0))

Add () for port_width.

>  
>  #define MTK_PROTECT_PA_ALIGN			256
>  
> @@ -291,12 +293,13 @@ static irqreturn_t mtk_iommu_isr(int irq, void
> *dev_id)
>  		fault_pa |= (u64)pa34_32 << 32;
>  	}
>  
> -	fault_port = F_MMU_INT_ID_PORT_ID(regval);
> +	fault_port = F_MMU_INT_ID_PORT_ID(regval, data->plat_data-
> >port_width);
>  	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
>  		fault_larb = F_MMU_INT_ID_COMM_ID(regval);
>  		sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
>  	} else {
> -		fault_larb = F_MMU_INT_ID_LARB_ID(regval);
> +		fault_larb = F_MMU_INT_ID_LARB_ID(regval,
> +						  data->plat_data-
> >port_width);
>  	}
>  	fault_larb = data->plat_data-
> >larbid_remap[fault_larb][sub_comm];
>  
> @@ -1034,6 +1037,7 @@ static const struct mtk_iommu_plat_data
> mt2712_data = {
>  	.iova_region  = single_domain,
>  	.iova_region_nr = ARRAY_SIZE(single_domain),
>  	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
> +	.port_width   = 5,
>  };
>  
>  static const struct mtk_iommu_plat_data mt6779_data = {
> @@ -1043,6 +1047,7 @@ static const struct mtk_iommu_plat_data
> mt6779_data = {
>  	.iova_region   = single_domain,
>  	.iova_region_nr = ARRAY_SIZE(single_domain),
>  	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> +	.port_width    = 5,
>  };
>  
>  static const struct mtk_iommu_plat_data mt8167_data = {
> @@ -1052,6 +1057,7 @@ static const struct mtk_iommu_plat_data
> mt8167_data = {
>  	.iova_region  = single_domain,
>  	.iova_region_nr = ARRAY_SIZE(single_domain),
>  	.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
> +	.port_width   = 5,
>  };
>  
>  static const struct mtk_iommu_plat_data mt8173_data = {
> @@ -1062,6 +1068,7 @@ static const struct mtk_iommu_plat_data
> mt8173_data = {
>  	.iova_region  = single_domain,
>  	.iova_region_nr = ARRAY_SIZE(single_domain),
>  	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear
> mapping. */
> +	.port_width   = 5,
>  };
>  
>  static const struct mtk_iommu_plat_data mt8183_data = {
> @@ -1071,6 +1078,7 @@ static const struct mtk_iommu_plat_data
> mt8183_data = {
>  	.iova_region  = single_domain,
>  	.iova_region_nr = ARRAY_SIZE(single_domain),
>  	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
> +	.port_width   = 5,
>  };
>  
>  static const struct mtk_iommu_plat_data mt8192_data = {
> @@ -1082,6 +1090,7 @@ static const struct mtk_iommu_plat_data
> mt8192_data = {
>  	.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
>  	.larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
>  			   {0, 14, 16}, {0, 13, 18, 17}},
> +	.port_width     = 5,
>  };
>  
>  static const struct of_device_id mtk_iommu_of_ids[] = {
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index b742432220c5..84cecaf6d61c 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -54,6 +54,7 @@ struct mtk_iommu_plat_data {
>  	enum mtk_iommu_plat m4u_plat;
>  	u32                 flags;
>  	u32                 inv_sel_reg;
> +	u8                  port_width;

Please help rename to int_id_port_width for more detailed from the
register name (REG_MMU0_INT_ID).

>  
>  	unsigned int				iova_region_nr;
>  	const struct mtk_iommu_iova_region	*iova_region;
> -- 
> 2.36.1
>