[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <BY5PR02MB69471153D6BBAC2197A7AFD6A5A19@BY5PR02MB6947.namprd02.prod.outlook.com>
Date: Fri, 3 Jun 2022 04:52:18 +0000
From: Bharat Kumar Gogada <bharatku@...inx.com>
To: Rob Herring <robh@...nel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
Michal Simek <michals@...inx.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
> Subject: Re: [PATCH v2] dt-bindings: PCI: xilinx-cpm: Fix reg property order
>
> On Mon, 16 May 2022 15:52:17 +0530, Bharat Kumar Gogada wrote:
> > All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg.
> >
> > This order is also suggested by node name which is pcie@...10000 which
> > suggests that cpm_slcr register should be the first.
> >
> > Driver itself is using devm_platform_ioremap_resource_byname() for
> > both names that's why there is no functional change even on
> > description which are using current order.
> >
> > But still prefer to change order to cover currently used description.
> > Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM
> > Root Port")
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
> > ---
> > .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 10 +++++-----
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
>
> Applied, thanks!
Thanks Rob.
Powered by blists - more mailing lists