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Message-ID: <CAAhV-H5Hi_gYvrO6DAGGA=OVExunCubNpDBdkRBxFxiP1APAKw@mail.gmail.com>
Date: Fri, 3 Jun 2022 13:27:00 +0800
From: Huacai Chen <chenhuacai@...il.com>
To: Bagas Sanjaya <bagasdotme@...il.com>
Cc: Huacai Chen <chenhuacai@...ngson.cn>,
Arnd Bergmann <arnd@...db.de>,
Andy Lutomirski <luto@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
Andrew Morton <akpm@...ux-foundation.org>,
David Airlie <airlied@...ux.ie>,
Jonathan Corbet <corbet@....net>,
Linus Torvalds <torvalds@...ux-foundation.org>,
linux-arch <linux-arch@...r.kernel.org>,
"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
Xuefeng Li <lixuefeng@...ngson.cn>,
Yanteng Si <siyanteng@...ngson.cn>,
Guo Ren <guoren@...nel.org>, Xuerui Wang <kernel@...0n.name>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
Stephen Rothwell <sfr@...b.auug.org.au>,
WANG Xuerui <git@...0n.name>
Subject: Re: [PATCH V14 03/24] Documentation: LoongArch: Add basic documentations
Hi, Bagas,
On Fri, Jun 3, 2022 at 9:45 AM Bagas Sanjaya <bagasdotme@...il.com> wrote:
>
> On Thu, Jun 02, 2022 at 07:51:20PM +0800, Huacai Chen wrote:
> > +Legacy IRQ model
> > +================
> > +
> > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
> > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
> > +to LIOINTC, and then CPUINTC.
> > +
> > + +---------------------------------------------+
> > + |:: |
> > + | |
> > + | +-----+ +---------+ +-------+ |
> > + | | IPI | --> | CPUINTC | <-- | Timer | |
> > + | +-----+ +---------+ +-------+ |
> > + | ^ |
> > + | | |
> > + | +---------+ +-------+ |
> > + | | LIOINTC | <-- | UARTs | |
> > + | +---------+ +-------+ |
> > + | ^ |
> > + | | |
> > + | +-----------+ |
> > + | | HTVECINTC | |
> > + | +-----------+ |
> > + | ^ ^ |
> > + | | | |
> > + | +---------+ +---------+ |
> > + | | PCH-PIC | | PCH-MSI | |
> > + | +---------+ +---------+ |
> > + | ^ ^ ^ |
> > + | | | | |
> > + | +---------+ +---------+ +---------+ |
> > + | | PCH-LPC | | Devices | | Devices | |
> > + | +---------+ +---------+ +---------+ |
> > + | ^ |
> > + | | |
> > + | +---------+ |
> > + | | Devices | |
> > + | +---------+ |
> > + | |
> > + | |
> > + +---------------------------------------------+
> > +
> > +Extended IRQ model
> > +==================
> > +
> > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
> > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
> > +to CPUINTC directly.
> > +
> > + +--------------------------------------------------------+
> > + |:: |
> > + | |
> > + | +-----+ +---------+ +-------+ |
> > + | | IPI | --> | CPUINTC | <-- | Timer | |
> > + | +-----+ +---------+ +-------+ |
> > + | ^ ^ |
> > + | | | |
> > + | +---------+ +---------+ +-------+ |
> > + | | EIOINTC | | LIOINTC | <-- | UARTs | |
> > + | +---------+ +---------+ +-------+ |
> > + | ^ ^ |
> > + | | | |
> > + | +---------+ +---------+ |
> > + | | PCH-PIC | | PCH-MSI | |
> > + | +---------+ +---------+ |
> > + | ^ ^ ^ |
> > + | | | | |
> > + | +---------+ +---------+ +---------+ |
> > + | | PCH-LPC | | Devices | | Devices | |
> > + | +---------+ +---------+ +---------+ |
> > + | ^ |
> > + | | |
> > + | +---------+ |
> > + | | Devices | |
> > + | +---------+ |
> > + | |
> > + | |
> > + +--------------------------------------------------------+
> > +
>
> I think for consistency with other diagrams in Documentation/, just use
> literal code block, like:
>
> diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst
> index 35c962991283ff..3cfd528021de05 100644
> --- a/Documentation/loongarch/irq-chip-model.rst
> +++ b/Documentation/loongarch/irq-chip-model.rst
> @@ -24,40 +24,38 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
> to LIOINTC, and then CPUINTC.
>
> - +---------------------------------------------+
> - |:: |
> - | |
> - | +-----+ +---------+ +-------+ |
> - | | IPI | --> | CPUINTC | <-- | Timer | |
> - | +-----+ +---------+ +-------+ |
> - | ^ |
> - | | |
> - | +---------+ +-------+ |
> - | | LIOINTC | <-- | UARTs | |
> - | +---------+ +-------+ |
> - | ^ |
> - | | |
> - | +-----------+ |
> - | | HTVECINTC | |
> - | +-----------+ |
> - | ^ ^ |
> - | | | |
> - | +---------+ +---------+ |
> - | | PCH-PIC | | PCH-MSI | |
> - | +---------+ +---------+ |
> - | ^ ^ ^ |
> - | | | | |
> - | +---------+ +---------+ +---------+ |
> - | | PCH-LPC | | Devices | | Devices | |
> - | +---------+ +---------+ +---------+ |
> - | ^ |
> - | | |
> - | +---------+ |
> - | | Devices | |
> - | +---------+ |
> - | |
> - | |
> - +---------------------------------------------+
> + ::
> +
> + +-----+ +---------+ +-------+
> + | IPI | --> | CPUINTC | <-- | Timer |
> + +-----+ +---------+ +-------+
> + ^
> + |
> + +---------+ +-------+
> + | LIOINTC | <-- | UARTs |
> + +---------+ +-------+
> + ^
> + |
> + +-----------+
> + | HTVECINTC |
> + +-----------+
> + ^ ^
> + | |
> + +---------+ +---------+
> + | PCH-PIC | | PCH-MSI |
> + +---------+ +---------+
> + ^ ^ ^
> + | | |
> + +---------+ +---------+ +---------+
> + | PCH-LPC | | Devices | | Devices |
> + +---------+ +---------+ +---------+
> + ^
> + |
> + +---------+
> + | Devices |
> + +---------+
> +
> +
>
> Extended IRQ model
> ==================
> @@ -67,35 +65,33 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
> interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
> to CPUINTC directly.
>
> - +--------------------------------------------------------+
> - |:: |
> - | |
> - | +-----+ +---------+ +-------+ |
> - | | IPI | --> | CPUINTC | <-- | Timer | |
> - | +-----+ +---------+ +-------+ |
> - | ^ ^ |
> - | | | |
> - | +---------+ +---------+ +-------+ |
> - | | EIOINTC | | LIOINTC | <-- | UARTs | |
> - | +---------+ +---------+ +-------+ |
> - | ^ ^ |
> - | | | |
> - | +---------+ +---------+ |
> - | | PCH-PIC | | PCH-MSI | |
> - | +---------+ +---------+ |
> - | ^ ^ ^ |
> - | | | | |
> - | +---------+ +---------+ +---------+ |
> - | | PCH-LPC | | Devices | | Devices | |
> - | +---------+ +---------+ +---------+ |
> - | ^ |
> - | | |
> - | +---------+ |
> - | | Devices | |
> - | +---------+ |
> - | |
> - | |
> - +--------------------------------------------------------+
> + ::
> +
> + +-----+ +---------+ +-------+
> + | IPI | --> | CPUINTC | <-- | Timer |
> + +-----+ +---------+ +-------+
> + ^ ^
> + | |
> + +---------+ +---------+ +-------+
> + | EIOINTC | | LIOINTC | <-- | UARTs |
> + +---------+ +---------+ +-------+
> + ^ ^
> + | |
> + +---------+ +---------+
> + | PCH-PIC | | PCH-MSI |
> + +---------+ +---------+
> + ^ ^ ^
> + | | |
> + +---------+ +---------+ +---------+
> + | PCH-LPC | | Devices | | Devices |
> + +---------+ +---------+ +---------+
> + ^
> + |
> + +---------+
> + | Devices |
> + +---------+
> +
> +
>
> ACPI-related definitions
> ========================
>
> Otherwise, htmldocs builds successfully without any new warnings related
> to this patch series.
Thank you for your testing. In my environment (sphinx_2.4.4), with or
without the border both have no warnings. :)
And I think these are more pretty if we keep the border, especially
when formatted into PDF. How do you think?
Huacai
>
> Tested-by: Bagas Sanjaya <bagasdotme@...il.com>
>
> --
> An old man doll... just what I always wanted! - Clara
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