| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <5e57a1f3-1159-9277-5f8c-6ed0ad030a00@kernel.org>
Date: Fri, 3 Jun 2022 13:31:44 +0300
From: Georgi Djakov <djakov@...nel.org>
To: Chanwoo Choi <cw00.choi@...sung.com>,
Johnson Wang <johnson.wang@...iatek.com>, krzk+dt@...nel.org,
robh+dt@...nel.org, kyungmin.park@...sung.com
Cc: khilman@...nel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, jia-wei.chang@...iatek.com,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v6 1/2] dt-bindings: interconnect: Add MediaTek CCI
dt-bindings
On 3.06.22 3:39, Chanwoo Choi wrote:
> Hi Georgi,
>
> If you agree this dt-bidning into .../bindings/interconnect,
> I'll merge it. Could you please review it?
>
> On 5/27/22 8:00 PM, Johnson Wang wrote:
>> Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
>>
>> Signed-off-by: Jia-Wei Chang <jia-wei.chang@...iatek.com>
>> Signed-off-by: Johnson Wang <johnson.wang@...iatek.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>> Acked-by: Chanwoo Choi <cw00.choi@...sung.com>
>> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
Acked-by: Georgi Djakov <djakov@...nel.org>
Looks good to me. Thanks!
BR,
Georgi
>> ---
>> .../bindings/interconnect/mediatek,cci.yaml | 141 ++++++++++++++++++
>> MAINTAINERS | 1 +
>> 2 files changed, 142 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> new file mode 100644
>> index 000000000000..449c7c988229
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> @@ -0,0 +1,141 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://protect2.fireeye.com/v1/url?k=ad4ad61b-cc317c8c-ad4b5d54-74fe4860001d-01f34b7b1b45f9dd&q=1&e=81fe0992-6204-4794-b412-8ba4ca747e10&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Finterconnect%2Fmediatek%2Ccci.yaml%23
>> +$schema: https://protect2.fireeye.com/v1/url?k=a032f6c0-c1495c57-a0337d8f-74fe4860001d-83ce1b32f63b7f35&q=1&e=81fe0992-6204-4794-b412-8ba4ca747e10&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
>> +
>> +maintainers:
>> + - Jia-Wei Chang <jia-wei.chang@...iatek.com>
>> + - Johnson Wang <johnson.wang@...iatek.com>
>> +
>> +description: |
>> + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
>> + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
>> + hardware. It can also optimize the voltage to reduce the power consumption.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - mediatek,mt8183-cci
>> + - mediatek,mt8186-cci
>> +
>> + clocks:
>> + items:
>> + - description:
>> + The multiplexer for clock input of the bus.
>> + - description:
>> + A parent of "bus" clock which is used as an intermediate clock source
>> + when the original clock source (PLL) is under transition and not
>> + stable yet.
>> +
>> + clock-names:
>> + items:
>> + - const: cci
>> + - const: intermediate
>> +
>> + operating-points-v2: true
>> + opp-table: true
>> +
>> + proc-supply:
>> + description:
>> + Phandle of the regulator for CCI that provides the supply voltage.
>> +
>> + sram-supply:
>> + description:
>> + Phandle of the regulator for sram of CCI that provides the supply
>> + voltage. When it is present, the implementation needs to do
>> + "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
>> + SoC specific needs. When absent, the voltage scaling flow is handled by
>> + hardware, hence no software "voltage tracking" is needed.
>> +
>> +required:
>> + - compatible
>> + - clocks
>> + - clock-names
>> + - operating-points-v2
>> + - proc-supply
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/mt8183-clk.h>
>> + cci: cci {
>> + compatible = "mediatek,mt8183-cci";
>> + clocks = <&mcucfg CLK_MCU_BUS_SEL>,
>> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
>> + clock-names = "cci", "intermediate";
>> + operating-points-v2 = <&cci_opp>;
>> + proc-supply = <&mt6358_vproc12_reg>;
>> + };
>> +
>> + cci_opp: opp-table-cci {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> + opp2_00: opp-273000000 {
>> + opp-hz = /bits/ 64 <273000000>;
>> + opp-microvolt = <650000>;
>> + };
>> + opp2_01: opp-338000000 {
>> + opp-hz = /bits/ 64 <338000000>;
>> + opp-microvolt = <687500>;
>> + };
>> + opp2_02: opp-403000000 {
>> + opp-hz = /bits/ 64 <403000000>;
>> + opp-microvolt = <718750>;
>> + };
>> + opp2_03: opp-463000000 {
>> + opp-hz = /bits/ 64 <463000000>;
>> + opp-microvolt = <756250>;
>> + };
>> + opp2_04: opp-546000000 {
>> + opp-hz = /bits/ 64 <546000000>;
>> + opp-microvolt = <800000>;
>> + };
>> + opp2_05: opp-624000000 {
>> + opp-hz = /bits/ 64 <624000000>;
>> + opp-microvolt = <818750>;
>> + };
>> + opp2_06: opp-689000000 {
>> + opp-hz = /bits/ 64 <689000000>;
>> + opp-microvolt = <850000>;
>> + };
>> + opp2_07: opp-767000000 {
>> + opp-hz = /bits/ 64 <767000000>;
>> + opp-microvolt = <868750>;
>> + };
>> + opp2_08: opp-845000000 {
>> + opp-hz = /bits/ 64 <845000000>;
>> + opp-microvolt = <893750>;
>> + };
>> + opp2_09: opp-871000000 {
>> + opp-hz = /bits/ 64 <871000000>;
>> + opp-microvolt = <906250>;
>> + };
>> + opp2_10: opp-923000000 {
>> + opp-hz = /bits/ 64 <923000000>;
>> + opp-microvolt = <931250>;
>> + };
>> + opp2_11: opp-962000000 {
>> + opp-hz = /bits/ 64 <962000000>;
>> + opp-microvolt = <943750>;
>> + };
>> + opp2_12: opp-1027000000 {
>> + opp-hz = /bits/ 64 <1027000000>;
>> + opp-microvolt = <975000>;
>> + };
>> + opp2_13: opp-1092000000 {
>> + opp-hz = /bits/ 64 <1092000000>;
>> + opp-microvolt = <1000000>;
>> + };
>> + opp2_14: opp-1144000000 {
>> + opp-hz = /bits/ 64 <1144000000>;
>> + opp-microvolt = <1025000>;
>> + };
>> + opp2_15: opp-1196000000 {
>> + opp-hz = /bits/ 64 <1196000000>;
>> + opp-microvolt = <1050000>;
>> + };
>> + };
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 41c9c8f2b96d..7239f0e0c47b 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -5735,6 +5735,7 @@ L: linux-pm@...r.kernel.org
>> S: Maintained
>> T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
>> F: Documentation/devicetree/bindings/devfreq/
>> +F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>> F: drivers/devfreq/
>> F: include/linux/devfreq.h
>> F: include/trace/events/devfreq.h
>>
>
>
Powered by blists - more mailing lists