linux-kernel - Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <87wndu3tff.wl-maz@kernel.org>
Date:   Mon, 06 Jun 2022 12:47:16 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Dragan Mladjenovic <Dragan.Mladjenovic@...mia.com>
Cc:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Chao-ying Fu <cfu@...ecomp.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Greg Ungerer <gerg@...nel.org>,
        Hauke Mehrtens <hauke@...ke-m.de>,
        Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        Paul Burton <paulburton@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Tiezhu Yang <yangtiezhu@...ngson.cn>,
        Dragan Mladjenovic <dragan.mladjenovic@...mia.com>
Subject: Re: [PATCH v2 06/12] irqchip: mips-gic: Multi-cluster support

On Wed, 25 May 2022 13:10:24 +0100,
Dragan Mladjenovic <Dragan.Mladjenovic@...mia.com> wrote:
> 
> From: Paul Burton <paulburton@...nel.org>
> 
> The MIPS I6500 CPU & CM (Coherence Manager) 3.5 introduce the concept of
> multiple clusters to the system. In these systems each cluster contains
> its own GIC, so the GIC isn't truly global any longer. We do have the
> ability to access registers in the GICs of remote clusters using a
> redirect register block much like the redirect register blocks provided
> by the CM & CPC, and configured through the same GCR_REDIRECT register
> that we our mips_cm_lock_other() abstraction builds upon.
> 
> It is expected that external interrupts are connected identically to all
> clusters. That is, if we have a device providing an interrupt connected
> to GIC interrupt pin 0 then it should be connected to pin 0 of every GIC
> in the system. This simplifies things somewhat by allowing us for the
> most part to treat the GIC as though it is still truly global, so long
> as we take care to configure interrupts in the cluster that we want them
> affine to.

I can see how this can work for level interrupts, but how does this
work for edge interrupts? Is there any guarantee that the interrupt
will be discarded if routed to a cluster where it isn't configured?

Otherwise, I can imagine plenty of spurious interrupts on affinity
change.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.