linux-kernel - RE: [PATCH v2 3/5] ARM: dts: aspeed: Add HACE device controller node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <HK0PR06MB3202698F2E93BE1CF2C9626380A59@HK0PR06MB3202.apcprd06.prod.outlook.com>
Date:   Tue, 7 Jun 2022 03:59:48 +0000
From:   Neal Liu <neal_liu@...eedtech.com>
To:     Dhananjay Phadke <dphadke@...ux.microsoft.com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        "David S . Miller" <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Joel Stanley <joel@....id.au>,
        Andrew Jeffery <andrew@...id.au>,
        Johnny Huang <johnny_huang@...eedtech.com>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
        BMC-SW <BMC-SW@...eedtech.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v2 3/5] ARM: dts: aspeed: Add HACE device controller node

> On 6/5/2022 11:49 PM, Neal Liu wrote:
> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> > b/arch/arm/boot/dts/aspeed-g6.dtsi
> > index 3d5ce9da42c3..371d2a6b56ef 100644
> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> > @@ -304,6 +304,14 @@ apb {
> >   			#size-cells = <1>;
> >   			ranges;
> >
> > +			hace: crypto@...d0000 {
> > +				compatible = "aspeed,ast2600-hace";
> > +				reg = <0x1e6d0000 0x200>;
> > +				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
> > +				resets = <&syscon ASPEED_RESET_HACE>;
> 
> Shouldn't the left side be also 'crypto', see existing crypto nodes in
> arch/arm64/dts for example.
> 
> 			crypto: crypto@...d0000 {
> 				...
> 
> Regards,
> Dhananjay

It's a naming preference. "hace" is our hash & crypto hardware engine naming.
And we also have other crypto engines will be upstream soon.
So I prefer to keep this part, is that okay for you?

Thanks