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Date: Tue, 7 Jun 2022 13:52:38 -0400 From: Sasha Levin <sashal@...nel.org> To: linux-kernel@...r.kernel.org, stable@...r.kernel.org Cc: David Galiffi <David.Galiffi@....com>, Martin Leung <Martin.Leung@....com>, Qingqing Zhuo <qingqing.zhuo@....com>, Daniel Wheeler <daniel.wheeler@....com>, Alex Deucher <alexander.deucher@....com>, Sasha Levin <sashal@...nel.org>, harry.wentland@....com, sunpeng.li@....com, Rodrigo.Siqueira@....com, christian.koenig@....com, Xinhui.Pan@....com, airlied@...ux.ie, daniel@...ll.ch, Hansen.Dsouza@....com, Charlene.Liu@....com, HaoPing.Liu@....com, baihaowen@...zu.com, dillon.varone@....com, alex.hung@....com, amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org Subject: [PATCH AUTOSEL 5.17 41/60] drm/amd/display: Check if modulo is 0 before dividing. From: David Galiffi <David.Galiffi@....com> [ Upstream commit 49947b906a6bd9668eaf4f9cf691973c25c26955 ] [How & Why] If a value of 0 is read, then this will cause a divide-by-0 panic. Reviewed-by: Martin Leung <Martin.Leung@....com> Acked-by: Qingqing Zhuo <qingqing.zhuo@....com> Signed-off-by: David Galiffi <David.Galiffi@....com> Tested-by: Daniel Wheeler <daniel.wheeler@....com> Signed-off-by: Alex Deucher <alexander.deucher@....com> Signed-off-by: Sasha Levin <sashal@...nel.org> --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 2c7eb982eabc..054823d12403 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1013,9 +1013,12 @@ static bool get_pixel_clk_frequency_100hz( * not be programmed equal to DPREFCLK */ modulo_hz = REG_READ(MODULO[inst]); - *pixel_clk_khz = div_u64((uint64_t)clock_hz* - clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, - modulo_hz); + if (modulo_hz) + *pixel_clk_khz = div_u64((uint64_t)clock_hz* + clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, + modulo_hz); + else + *pixel_clk_khz = 0; } else { /* NOTE: There is agreement with VBIOS here that MODULO is * programmed equal to DPREFCLK, in which case PHASE will be -- 2.35.1
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