linux-kernel - [PATCH 5.17 473/772] ARM: dts: stm32: Fix PHY post-reset delay on Avenger96

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Message-Id: <20220607165002.934367219@linuxfoundation.org>
Date:   Tue,  7 Jun 2022 19:01:05 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Marek Vasut <marex@...x.de>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Patrice Chotard <patrice.chotard@...s.st.com>,
        Patrick Delaunay <patrick.delaunay@...s.st.com>,
        linux-stm32@...md-mailman.stormreply.com,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.17 473/772] ARM: dts: stm32: Fix PHY post-reset delay on Avenger96

From: Marek Vasut <marex@...x.de>

[ Upstream commit ef2d90708883f4025a801feb0ba8411a7a4387e1 ]

Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING
Note 2: After the de-assertion of reset, wait a minimum of 100 μs before
starting programming on the MIIM (MDC/MDIO) interface.

Add 1ms post-reset delay to guarantee this figure.

Fixes: 010ca9fe500bf ("ARM: dts: stm32: Add missing ethernet PHY reset on AV96")
Signed-off-by: Marek Vasut <marex@...x.de>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>
Cc: Patrice Chotard <patrice.chotard@...s.st.com>
Cc: Patrick Delaunay <patrick.delaunay@...s.st.com>
Cc: linux-stm32@...md-mailman.stormreply.com
To: linux-arm-kernel@...ts.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
index 6885948f3024..8eb51d84b698 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -141,6 +141,7 @@
 		compatible = "snps,dwmac-mdio";
 		reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
 		reset-delay-us = <1000>;
+		reset-post-delay-us = <1000>;
 
 		phy0: ethernet-phy@7 {
 			reg = <7>;
-- 
2.35.1