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Message-Id: <20220607111625.1845393-4-abel.vesa@nxp.com>
Date: Tue, 7 Jun 2022 14:16:16 +0300
From: Abel Vesa <abel.vesa@....com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Joakim Zhang <qiangqing.zhang@....com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
NXP Linux Team <linux-imx@....com>
Cc: Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
<netdev@...r.kernel.org>, linux-phy@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-usb@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Dong Aisheng <aisheng.dong@....com>,
Jacky Bai <ping.bai@....com>
Subject: [PATCH v9 03/12] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
From: Jacky Bai <ping.bai@....com>
Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
compared to i.MX8QXP.
Signed-off-by: Jacky Bai <ping.bai@....com>
Signed-off-by: Abel Vesa <abel.vesa@....com>
---
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..8a91eb33b4ef
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&ddr_subsys {
+ db_ipg_clk: clock-db-ipg@0 {
+ compatible = "fixed-clock";
+ reg = <0 0>;
+ #clock-cells = <0>;
+ clock-frequency = <456000000>;
+ clock-output-names = "db_ipg_clk";
+ };
+
+ db_pmu0: db-pmu@...40000 {
+ compatible = "fsl,imx8dxl-db-pmu";
+ reg = <0x5ca40000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_0>,
+ <&db_pmu0_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "ipg", "cnt";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+
+ db_pmu0_lpcg: clock-controller@...e0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5cae0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>,
+ <IMX_LPCG_CLK_1>;
+ clock-output-names = "perf_lpcg_cnt_clk",
+ "perf_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+};
--
2.34.3
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