linux-kernel - [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

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Message-Id: <20220607131648.29439-4-nikita.shubin@maquefel.me>
Date:   Tue,  7 Jun 2022 16:16:46 +0300
From:   Nikita Shubin <nikita.shubin@...uefel.me>
To:     unlisted-recipients:; (no To-header on input)
Cc:     Genevieve Chan <genevieve.chan@...rfivetech.com>,
        João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>,
        Nikita Shubin <n.shubin@...ro.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        linux-kernel@...r.kernel.org (open list),
        linux-perf-users@...r.kernel.org (open list:PERFORMANCE EVENTS
        SUBSYSTEM),
        linux-riscv@...ts.infradead.org (open list:RISC-V ARCHITECTURE)
Subject: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

From: João Mário Domingos <joao.mario@...nico.ulisboa.pt>

The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.

Signed-off-by: João Mário Domingos <joao.mario@...nico.ulisboa.pt>
Tested-by: Nikita Shubin <n.shubin@...ro.com>
---
 tools/perf/pmu-events/arch/riscv/mapfile.csv  | 14 +++++++++++++
 .../pmu-events/arch/riscv/riscv-generic.json  | 20 +++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json

diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
new file mode 100644
index 000000000000..4f2aa199d9cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#		Variant[23:20] and Revision [3:0] should be zero.
+#	Version could be used to track version of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/riscv/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
new file mode 100644
index 000000000000..013e50efad99
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
@@ -0,0 +1,20 @@
+[
+  {
+    "PublicDescription": "CPU Cycles",
+    "EventCode": "0x00",
+    "EventName": "riscv_cycles",
+    "BriefDescription": "CPU cycles RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Time",
+      "EventCode": "0x01",
+      "EventName": "riscv_time",
+      "BriefDescription": "CPU time RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Instructions",
+      "EventCode": "0x02",
+      "EventName": "riscv_instret",
+      "BriefDescription": "CPU retired instructions RISC-V generic counter"
+  }
+]
\ No newline at end of file
-- 
2.35.1