linux-kernel - Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device tree

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Message-ID: <24ad8ba0-4244-1159-328d-12d0e67951e1@linaro.org>
Date:   Wed, 8 Jun 2022 12:21:54 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Tomer Maimon <tmaimon77@...il.com>, avifishman70@...il.com,
        tali.perry1@...il.com, joel@....id.au, venture@...gle.com,
        yuenn@...gle.com, benjaminfair@...gle.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        sboyd@...nel.org, p.zabel@...gutronix.de,
        gregkh@...uxfoundation.org, daniel.lezcano@...aro.org,
        tglx@...utronix.de, wim@...ux-watchdog.org, linux@...ck-us.net,
        catalin.marinas@....com, will@...nel.org, arnd@...db.de,
        olof@...om.net, jirislaby@...nel.org, shawnguo@...nel.org,
        bjorn.andersson@...aro.org, geert+renesas@...der.be,
        marcel.ziswiler@...adex.com, vkoul@...nel.org,
        biju.das.jz@...renesas.com, nobuhiro1.iwamatsu@...hiba.co.jp,
        robert.hancock@...ian.com, j.neuschaefer@....net, lkundrak@...sk
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-serial@...r.kernel.org,
        linux-watchdog@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device
 tree

On 08/06/2022 11:56, Tomer Maimon wrote:
> This adds initial device tree support for the
> Nuvoton NPCM845 Board Management controller (BMC) SoC family.
> 
> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
> have various peripheral IPs.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
> ---
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 197 ++++++++++++++++++
>  .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  76 +++++++
>  3 files changed, 274 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
>  create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 1ba04e31a438..7b107fa7414b 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += lg
>  subdir-y += marvell
>  subdir-y += mediatek
>  subdir-y += microchip
> +subdir-y += nuvoton
>  subdir-y += nvidia
>  subdir-y += qcom
>  subdir-y += realtek
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> new file mode 100644
> index 000000000000..97e108c50760
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@...oton.com
> +
> +#include <dt-bindings/clock/nuvoton,npcm8xx-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	interrupt-parent = <&gic>;
> +
> +	/* external reference clock */
> +	clk_refclk: clk-refclk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;

Ignored comment.

> +		clock-output-names = "refclk";
> +	};
> +
> +	/* external reference clock for cpu. float in normal operation */
> +	clk_sysbypck: clk-sysbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1000000000>;

Ignored comment.

> +		clock-output-names = "sysbypck";
> +	};
> +
> +	/* external reference clock for MC. float in normal operation */
> +	clk_mcbypck: clk-mcbypck {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <1050000000>;
> +		clock-output-names = "mcbypck";
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		gcr: gcr@...00000 {

Ignored comment.

> +			compatible = "nuvoton,npcm845-gcr", "syscon",
> +				"simple-mfd";

This is not a simple-mfd... I see original bindings defined it that way,
but why? I think they should be corrected - remove simple-mfd from the
bindings and DTS.


> +			reg = <0x0 0xf0800000 0x0 0x1000>;
> +		};
> +
> +		gic: interrupt-controller@...f9000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x0 0xdfff9000 0x0 0x1000>,
> +			      <0x0 0xdfffa000 0x0 0x2000>,
> +			      <0x0 0xdfffc000 0x0 0x2000>,
> +			      <0x0 0xdfffe000 0x0 0x2000>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			ppi-partitions {
> +				ppi_cluster0: interrupt-partition-0 {
> +					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> +				};
> +			};
> +		};
> +	};
> +
> +	ahb {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		rstc: rstc@...01000 {

Ignored comment.

Four comments from v1 ignored in this patch alone.

I'll stop reviewing, it is a waste of my time.

NAK for this change.

Best regards,
Krzysztof