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Message-ID: <1930a7b3-3637-9e3b-3dac-7baf034c7b7a@collabora.com>
Date: Wed, 8 Jun 2022 12:27:31 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Marijn Suijten <marijn.suijten@...ainline.org>,
Will Deacon <will@...nel.org>
Cc: Konrad Dybcio <konrad.dybcio@...ainline.org>,
~postmarketos/upstreaming@...ts.sr.ht,
linux-arm-msm@...r.kernel.org, bjorn.andersson@...aro.org,
linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux-foundation.org, martin.botka@...ainline.org,
angelogioacchino.delregno@...ainline.org,
jamipkettunen@...ainline.org, Rob Clark <robdclark@...il.com>,
Robin Murphy <robin.murphy@....com>,
Joerg Roedel <joro@...tes.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access
behavior
Il 06/06/22 00:06, Marijn Suijten ha scritto:
> On 2022-05-31 16:55:59, Will Deacon wrote:
>> On Fri, May 27, 2022 at 11:28:57PM +0200, Konrad Dybcio wrote:
>>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>>>
>>> As also stated in the arm-smmu driver, we must write the TCR before
>>> writing the TTBRs, since the TCR determines the access behavior of
>>> some fields.
>>
>> Where is this stated in the arm-smmu driver?
>>
>>>
>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>>> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
>>> ---
>>> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++++++------
>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
>>> index 1728d4d7fe25..75f353866c40 100644
>>> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
>>> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
>>> @@ -273,18 +273,18 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
>>> ctx->secure_init = true;
>>> }
>>>
>>> - /* TTBRs */
>>> - iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
>>> - pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
>>> - FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
>>> - iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
>>> -
>>> /* TCR */
>>> iommu_writel(ctx, ARM_SMMU_CB_TCR2,
>>> arm_smmu_lpae_tcr2(&pgtbl_cfg));
>>> iommu_writel(ctx, ARM_SMMU_CB_TCR,
>>> arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
>>>
>>> + /* TTBRs */
>>> + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
>>> + pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
>>> + FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
>>> + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
>>
>> I'd have thought that SCTLR.M would be clear here, so it shouldn't matter
>> what order we write these in.
>
> Having tested the series without this particular patch on 8976 (Sony
> Loire Suzu), it doesn't seem to matter indeed. I'll ask around if this
> "access behaviour" was observed on a different board/platform.
>
> - Marijn
On some platforms, the bootloader (and/or the hypervisor) is performing some
initialization of the IOMMU which, depending on the actual firmware version
that ran before booting Linux, may or may not leave SCTLR.M cleared.
Cheers,
Angelo
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