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Message-ID: <cf544be3-5c83-044d-95a7-62dd3695a3cc@huawei.com>
Date: Wed, 8 Jun 2022 16:51:14 +0100
From: John Garry <john.garry@...wei.com>
To: Nikita Shubin <nikita.shubin@...uefel.me>
CC: Genevieve Chan <genevieve.chan@...rfivetech.com>,
João Mário Domingos
<joao.mario@...nico.ulisboa.pt>,
Nikita Shubin <n.shubin@...ro.com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
"Namhyung Kim" <namhyung@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
"Palmer Dabbelt" <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
<linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>,
Atish Patra <atishp@...shpatra.org>
Subject: Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile
On 08/06/2022 15:41, Nikita Shubin wrote:
>>> mat:
>>> +# MIDR,Version,JSON/file/pathname,Type
>>> +#
>>> +# where
>>> +# MIDR Processor version
>> ARM, no?
I'm just saying that MIDR is for ARM, so please ensure that this term is
correct for riscv
> I've messed with --cc-cmd badly and didn't include every one in cover
> letter, sorry for that, attaching link to cover letter:
>
> https://lore.kernel.org/all/20220607131648.29439-1-nikita.shubin@maquefel.me/
>
> They are ARM inspired indeed.
>
>
>>> +# Variant[23:20] and Revision [3:0] should be zero.
>>> +# Version could be used to track version of JSON file
>>> +# but currently unused.
>>> +# JSON/file/pathname is the path to JSON file, relative
>>> +# to tools/perf/pmu-events/arch/riscv/.
>>> +# Type is core, uncore etc
>>> +#
>>> +#
>>> +#Family-model,Version,Filename,EventType
>>> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>>> b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
>>> 100644 index 000000000000..013e50efad99
>>> --- /dev/null
>>> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>> where or how are these referenced?
> Currently they are not referenced in this version of series at all,
ok, right, so a general kernel policy is not to include code which is
not referenced.
> their purpose is to be used like "ArchStdEvent".
>
> Through any RISCV implementation should have at least these 3 events.
Thanks,
John
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