| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 8 Jun 2022 19:49:19 +0300
From: Abel Vesa <abel.vesa@....com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Dmitry Torokhov <dmitry.torokhov@...il.com>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Dong Aisheng <aisheng.dong@....com>,
Shawn Guo <shawnguo@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Guenter Roeck <linux@...ck-us.net>
Cc: Stephen Boyd <sboyd@...nel.org>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
devicetree@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
NXP Linux Team <linux-imx@....com>,
linux-clk@...r.kernel.org, linux-input@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-rtc@...r.kernel.org,
linux-pm@...r.kernel.org, linux-watchdog@...r.kernel.org
Subject: [PATCH v2 01/10] dt-bindings: firmware: Add fsl,scu yaml file
In order to replace the fsl,scu txt file from bindings/arm/freescale,
we need to split it between the right subsystems. This patch adds the
fsl,scu.yaml in the firmware bindings folder. This one is only for
the main SCU node. The old txt file will be removed only after all
the child nodes have been properly switch to yaml.
Signed-off-by: Abel Vesa <abel.vesa@....com>
---
.../devicetree/bindings/firmware/fsl,scu.yaml | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
new file mode 100644
index 000000000000..d0610887e80c
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX System Controller Firmware (SCFW)
+
+maintainers:
+ - Shawn Guo <shawnguo@...nel.org>
+
+description: System Controller Device Node
+ The System Controller Firmware (SCFW) is a low-level system function
+ which runs on a dedicated Cortex-M core to provide power, clock, and
+ resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+ (QM, QP), and i.MX8QX (QXP, DX).
+ The AP communicates with the SC using a multi-ported MU module found
+ in the LSIO subsystem. The current definition of this MU module provides
+ 5 remote AP connections to the SC to support up to 5 execution environments
+ (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
+ with the LSIO DSC IP bus. The SC firmware will communicate with this MU
+ using the MSI bus.
+
+properties:
+ $nodename:
+ const: 'scu'
+
+ compatible:
+ const: fsl,imx-scu
+
+ clock-controller:
+ description: |
+ Clock controller node that provides the clocks controlled by the SCU
+
+ imx8qx-ocotp:
+ description: |
+ OCOTP controller node provided by the SCU
+
+ keys:
+ description: |
+ Keys provided by the SCU
+
+ mboxes:
+ description: |
+ $ref: /schemas/mailbox/fsl,mu.yaml
+ List of phandle of 4 MU channels for tx, 4 MU channels for
+ rx, and 1 optional MU channel for general interrupt.
+ All MU channels must be in the same MU instance.
+ Cross instances are not allowed. The MU instance can only
+ be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
+ to make sure use the one which is not conflict with other
+ execution environments. e.g. ATF.
+ minItems: 1
+ maxItems: 10
+
+ mbox-names:
+ description:
+ include "gip3" if want to support general MU interrupt.
+ minItems: 1
+ maxItems: 10
+
+ pinctrl:
+ description: |
+ Pin controller provided by the SCU
+
+ power-controller:
+ description: |
+ Power domains controller node that provides the power domains
+ controlled by the SCU
+
+ rtc:
+ description: |
+ RTC controller provided by the SCU
+
+ thermal-sensor:
+ description: |
+ Thermal sensor provided by the SCU
+
+ watchdog:
+ description: |
+ Watchdog controller provided by the SCU
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+ firmware {
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 0 1
+ &lsio_mu1 0 2
+ &lsio_mu1 0 3
+ &lsio_mu1 1 0
+ &lsio_mu1 1 1
+ &lsio_mu1 1 2
+ &lsio_mu1 1 3
+ &lsio_mu1 3 3>;
+
+ clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ };
+
+ pinctrl {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+ };
+
+ imx8qx-ocotp {
+ compatible = "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+ };
+
+ power-controller {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
+ rtc {
+ compatible = "fsl,imx8qxp-sc-rtc";
+ };
+
+ keys {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycodes = <KEY_POWER>;
+ };
+
+ watchdog {
+ compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
--
2.34.3
Powered by blists - more mailing lists