| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAC_TJvdKM4S1kSmr3jkOvFofjyg=ASibNqgiTJBTYP=We1S=fA@mail.gmail.com>
Date: Wed, 8 Jun 2022 11:17:31 -0700
From: Kalesh Singh <kaleshsingh@...gle.com>
To: Marc Zyngier <maz@...nel.org>
Cc: Mark Rutland <mark.rutland@....com>,
Mark Brown <broonie@...nel.org>, Will Deacon <will@...nel.org>,
Quentin Perret <qperret@...gle.com>,
Fuad Tabba <tabba@...gle.com>,
Suren Baghdasaryan <surenb@...gle.com>,
"T.J. Mercier" <tjmercier@...gle.com>,
"Cc: Android Kernel" <kernel-team@...roid.com>,
James Morse <james.morse@....com>,
Alexandru Elisei <alexandru.elisei@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Catalin Marinas <catalin.marinas@....com>,
Masami Hiramatsu <mhiramat@...nel.org>,
Alexei Starovoitov <ast@...nel.org>,
"Madhavan T. Venkataraman" <madvenka@...ux.microsoft.com>,
Peter Zijlstra <peterz@...radead.org>,
Andrew Jones <drjones@...hat.com>,
Zenghui Yu <yuzenghui@...wei.com>,
Keir Fraser <keirf@...gle.com>,
Kefeng Wang <wangkefeng.wang@...wei.com>,
Ard Biesheuvel <ardb@...nel.org>,
Oliver Upton <oupton@...gle.com>,
"moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
<linux-arm-kernel@...ts.infradead.org>,
kvmarm <kvmarm@...ts.cs.columbia.edu>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 4/5] KVM: arm64: Allocate shared stacktrace pages
On Wed, Jun 8, 2022 at 2:02 AM Marc Zyngier <maz@...nel.org> wrote:
>
> On Tue, 07 Jun 2022 17:50:46 +0100,
> Kalesh Singh <kaleshsingh@...gle.com> wrote:
> >
> > The nVHE hypervisor can use this shared area to dump its stacktrace
> > addresses on hyp_panic(). Symbolization and printing the stacktrace can
> > then be handled by the host in EL1 (done in a later patch in this series).
> >
> > Signed-off-by: Kalesh Singh <kaleshsingh@...gle.com>
> > ---
> > arch/arm64/include/asm/kvm_asm.h | 1 +
> > arch/arm64/kvm/arm.c | 34 ++++++++++++++++++++++++++++++++
> > arch/arm64/kvm/hyp/nvhe/setup.c | 11 +++++++++++
> > 3 files changed, 46 insertions(+)
> >
> > diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
> > index 2e277f2ed671..ad31ac68264f 100644
> > --- a/arch/arm64/include/asm/kvm_asm.h
> > +++ b/arch/arm64/include/asm/kvm_asm.h
> > @@ -174,6 +174,7 @@ struct kvm_nvhe_init_params {
> > unsigned long hcr_el2;
> > unsigned long vttbr;
> > unsigned long vtcr;
> > + unsigned long stacktrace_hyp_va;
> > };
> >
> > /* Translate a kernel address @ptr into its equivalent linear mapping */
> > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > index 400bb0fe2745..c0a936a7623d 100644
> > --- a/arch/arm64/kvm/arm.c
> > +++ b/arch/arm64/kvm/arm.c
> > @@ -50,6 +50,7 @@ DEFINE_STATIC_KEY_FALSE(kvm_protected_mode_initialized);
> > DECLARE_KVM_HYP_PER_CPU(unsigned long, kvm_hyp_vector);
> >
> > static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
> > +DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stacktrace_page);
>
> Why isn't this static, since the address is passed via the
> kvm_nvhe_init_params block?
In the subsequent patch the host will need to read and symbolize the
addresses that the hypervisor dumped, it's done in stacktrace.c
>
> > unsigned long kvm_arm_hyp_percpu_base[NR_CPUS];
> > DECLARE_KVM_NVHE_PER_CPU(struct kvm_nvhe_init_params, kvm_init_params);
> >
> > @@ -1554,6 +1555,7 @@ static void cpu_prepare_hyp_mode(int cpu)
> > tcr |= (idmap_t0sz & GENMASK(TCR_TxSZ_WIDTH - 1, 0)) << TCR_T0SZ_OFFSET;
> > params->tcr_el2 = tcr;
> >
> > + params->stacktrace_hyp_va = kern_hyp_va(per_cpu(kvm_arm_hyp_stacktrace_page, cpu));
> > params->pgd_pa = kvm_mmu_get_httbr();
> > if (is_protected_kvm_enabled())
> > params->hcr_el2 = HCR_HOST_NVHE_PROTECTED_FLAGS;
> > @@ -1845,6 +1847,7 @@ static void teardown_hyp_mode(void)
> > free_hyp_pgds();
> > for_each_possible_cpu(cpu) {
> > free_page(per_cpu(kvm_arm_hyp_stack_page, cpu));
> > + free_page(per_cpu(kvm_arm_hyp_stacktrace_page, cpu));
> > free_pages(kvm_arm_hyp_percpu_base[cpu], nvhe_percpu_order());
> > }
> > }
> > @@ -1936,6 +1939,23 @@ static int init_hyp_mode(void)
> > per_cpu(kvm_arm_hyp_stack_page, cpu) = stack_page;
> > }
> >
> > + /*
> > + * Allocate stacktrace pages for Hypervisor-mode.
> > + * This is used by the hypervisor to share its stacktrace
> > + * with the host on a hyp_panic().
> > + */
> > + for_each_possible_cpu(cpu) {
> > + unsigned long stacktrace_page;
> > +
> > + stacktrace_page = __get_free_page(GFP_KERNEL);
> > + if (!stacktrace_page) {
> > + err = -ENOMEM;
> > + goto out_err;
> > + }
> > +
> > + per_cpu(kvm_arm_hyp_stacktrace_page, cpu) = stacktrace_page;
>
> I have the same feeling as with the overflow stack. This is
> potentially a huge amount of memory: on my test box, with 64k pages,
> this is a whole 10MB that I give away for something that is only a
> debug facility.
>
> Can this somehow be limited? I don't see it being less than a page as
> a problem, as the memory is always shared back with EL1 in the case of
> pKVM (and normal KVM doesn't have that problem anyway).
>
> Alternatively, this should be restricted to pKVM. With normal nVHE,
> the host should be able to parse the EL2 stack directly with some
> offsetting. Actually, this is probably the best option.
In a previous approach we had something similar to what you propose
(unwinding in el1) [1]. But doesn't work for our production use case
with protected mode since it disabled the stage 2 protection. We could
do the split and take a different approach for the protected and
unprotected mode, but I'm not sure if it is worth the extra
complexity? If it is the memory usage you are concerned with, it could
be reduced to half of the current stack size (page size) [2], if we
want to retain all frames. But we could also have some max depth, say
like 16? One downside being that it could make stack overflows more
challenging to root cause.
[1] https://lore.kernel.org/lkml/20220224051439.640768-8-kaleshsingh@google.com/
[2] https://lore.kernel.org/r/CAC_TJvdCuGNEJC4M+bV6o48CSJRs_4GEUb3iiP_4ro79q=KesA@mail.gmail.com/
Thanks
Kalesh
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
Powered by blists - more mailing lists