linux-kernel - Re: [PATCH v2 07/20] clk: npcm8xx: add clock controller

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Message-Id: <20220609221433.B8990C34114@smtp.kernel.org>
Date:   Thu, 09 Jun 2022 15:14:31 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Tomer Maimon <tmaimon77@...il.com>, arnd@...db.de,
        avifishman70@...il.com, benjaminfair@...gle.com,
        biju.das.jz@...renesas.com, bjorn.andersson@...aro.org,
        catalin.marinas@....com, daniel.lezcano@...aro.org,
        geert+renesas@...der.be, gregkh@...uxfoundation.org,
        j.neuschaefer@....net, jirislaby@...nel.org, joel@....id.au,
        krzysztof.kozlowski+dt@...aro.org, linux@...ck-us.net,
        lkundrak@...sk, marcel.ziswiler@...adex.com,
        mturquette@...libre.com, nobuhiro1.iwamatsu@...hiba.co.jp,
        olof@...om.net, p.zabel@...gutronix.de, robert.hancock@...ian.com,
        robh+dt@...nel.org, shawnguo@...nel.org, tali.perry1@...il.com,
        tglx@...utronix.de, venture@...gle.com, vkoul@...nel.org,
        will@...nel.org, wim@...ux-watchdog.org, yuenn@...gle.com
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-serial@...r.kernel.org,
        linux-watchdog@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Tomer Maimon <tmaimon77@...il.com>
Subject: Re: [PATCH v2 07/20] clk: npcm8xx: add clock controller

Quoting Tomer Maimon (2022-06-08 02:56:10)
> diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> new file mode 100644
> index 000000000000..40340c3611b5
> --- /dev/null
> +++ b/drivers/clk/clk-npcm8xx.c
> @@ -0,0 +1,756 @@
[...]
> +
> +#define PLLCON_LOKI    BIT(31)
> +#define PLLCON_LOKS    BIT(30)
> +#define PLLCON_FBDV    GENMASK(27, 16)
> +#define PLLCON_OTDV2   GENMASK(15, 13)
> +#define PLLCON_PWDEN   BIT(12)
> +#define PLLCON_OTDV1   GENMASK(10, 8)
> +#define PLLCON_INDV    GENMASK(5, 0)
> +
> +static unsigned long npcm8xx_clk_pll_recalc_rate(struct clk_hw *hw,
> +                                                unsigned long parent_rate)
> +{
> +       struct npcm8xx_clk_pll *pll = to_npcm8xx_clk_pll(hw);
> +       unsigned long fbdv, indv, otdv1, otdv2;
> +       unsigned int val;
> +       u64 ret;
> +
> +       if (parent_rate == 0) {
> +               pr_debug("%s: parent rate is zero", __func__);

Missing newline.

> +               return 0;
> +       }
> +
> +       val = readl_relaxed(pll->pllcon);
> +
> +       indv = FIELD_GET(PLLCON_INDV, val);