lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <39a607ee-180e-b261-46f9-349c70294f4e@quicinc.com>
Date:   Thu, 9 Jun 2022 10:44:33 +0530
From:   Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
To:     Stephen Boyd <swboyd@...omium.org>, <agross@...nel.org>,
        <alsa-devel@...a-project.org>, <bgoswami@...cinc.com>,
        <bjorn.andersson@...aro.org>, <broonie@...nel.org>,
        <devicetree@...r.kernel.org>, <judyhsiao@...omium.org>,
        <lgirdwood@...il.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <perex@...ex.cz>,
        <quic_plai@...cinc.com>, <quic_rohkumar@...cinc.com>,
        <robh+dt@...nel.org>, <srinivas.kandagatla@...aro.org>,
        <tiwai@...e.com>, <vkoul@...nel.org>
Subject: Re: [PATCH v3 2/2] ASoC: qcom: soundwire: Add software clock gating
 requirement check


On 6/9/2022 12:59 AM, Stephen Boyd wrote:
Thanks for Your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2022-06-08 07:02:09)
>> Validate software clock gating required or not and do software
>> clock gating on hclk if soundwire is operational and keep it
>> running by adding flag in private dat structure.
>> This is to avoid conflict between older architectures,
>> where software clock gating is not required and on latest
>> architectues, where software clock gating is mandatory.
> This talks about software clock gating but the code is getting a reset
> and asserting it. Is that because the power on reset value of the clock
> gating is to have hardware clock gating disabled, but some earlier code
> is enabling hardware clock gating?

Yes Stephen. By Default this resets to HW controlled. As such there is 
no specific code

for enabling hardware clock gating, as these CGCR registers default 
setting is HW control.

>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
>> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
>> ---
>>   drivers/soundwire/qcom.c | 27 ++++++++++++++++++++-------
>>   1 file changed, 20 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
>> index 38c3bf5..ebd7479 100644
>> --- a/drivers/soundwire/qcom.c
>> +++ b/drivers/soundwire/qcom.c
>> @@ -659,7 +665,8 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
>>          val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
>>          val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
>>
>> -       reset_control_reset(ctrl->audio_cgcr);
>> +       if (ctrl->audio_cgcr)
>> +               reset_control_reset(ctrl->audio_cgcr);
>>
>>          ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
>>
>> @@ -1494,7 +1506,8 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev)
>>                  qcom_swrm_get_device_status(ctrl);
>>                  sdw_handle_slave_status(&ctrl->bus, ctrl->status);
>>          } else {
>> -               reset_control_reset(ctrl->audio_cgcr);
>> +               if (ctrl->audio_cgcr)
>> +                       reset_control_reset(ctrl->audio_cgcr);
> reset_control_reset() is a no-op if the pointer is NULL so the if
> condition is not necessary in the above two statements.
Okay. revert this NULL check here.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ